Merge pull request #214 from anthony-zy/add_zbb_check_macro

RISC-V: gate __builtin_ctzll behind Zbb to avoid 10 % slowdown

CMakeLists.txt

@@ -155,10 +155,20 @@ int main() {
   return __builtin_expect(0, 1);
 }" HAVE_BUILTIN_EXPECT)
 
+# Check if the built-in __builtin_ctz (count trailing zeros) is available.
+# Require either a non-RISC-V target, or a RISC-V core that implements
+# the Zbb bit-manipulation extension where ctz is guaranteed.
 check_cxx_source_compiles("
-int main() {
+#ifdef __riscv
-  return __builtin_ctzll(0);
+  #ifdef __riscv_zbb
-}" HAVE_BUILTIN_CTZ)
+    int main() { return __builtin_ctzll(0); }
+  #else
+    #error \"ZBB not enabled in current config\"
+  #endif
+#else
+  int main() { return __builtin_ctzll(0); }
+#endif
+" HAVE_BUILTIN_CTZ)
 
 check_cxx_source_compiles("
 int main() {

snappy-stubs-internal.h

@@ -304,8 +304,8 @@ class Bits {
   void operator=(const Bits&);
 };
 
+// In RISC-V,  CLZ  is supported by instructions from the ZBB bit-manipulation extension.
 #if HAVE_BUILTIN_CTZ
-
 inline int Bits::Log2FloorNonZero(uint32_t n) {
   assert(n != 0);
   // (31 ^ x) is equivalent to (31 - x) for x in [0, 31]. An easy proof
@@ -393,6 +393,7 @@ inline int Bits::FindLSBSetNonZero(uint32_t n) {
 
 #endif  // End portable versions.
 
+// In RISC-V,  CLZ  is supported by instructions from the ZBB bit-manipulation extension.
 #if HAVE_BUILTIN_CTZ
 
 inline int Bits::FindLSBSetNonZero64(uint64_t n) {