diff --git a/tools/ppc-manual/alu/addi.md b/tools/ppc-manual/alu/addi.md index ca2a42fb..e9e980d8 100644 --- a/tools/ppc-manual/alu/addi.md +++ b/tools/ppc-manual/alu/addi.md @@ -112,7 +112,7 @@ int InstrEmit_addi(PPCHIRBuilder& f, const InstrData& i) { - [`addis`](addis.md) — same encoding family but the immediate is shifted left by 16 bits. Together they build any 32-bit constant or PC-relative address. - [`addic`](addic.md), [`addicx`](addicx.md) — D-form adds that **do** set `XER[CA]` (and CR0 for the record form). - [`addx`](addx.md) — the register-register form. -- [`subfic`](subfic.md) — reverse-subtract immediate (`imm − RA`) with carry. +- [`subfic`](subficx.md) — reverse-subtract immediate (`imm − RA`) with carry. - [`ori`](ori.md), [`oris`](oris.md) — the alternative D-form constant-building instructions (but these don't add, they OR). ## IBM Reference diff --git a/tools/ppc-manual/alu/addic.md b/tools/ppc-manual/alu/addic.md index 3065fd81..4df3f11a 100644 --- a/tools/ppc-manual/alu/addic.md +++ b/tools/ppc-manual/alu/addic.md @@ -116,7 +116,7 @@ int InstrEmit_addic(PPCHIRBuilder& f, const InstrData& i) { - [`addi`](addi.md) — D-form add immediate without `XER[CA]`. - [`addis`](addis.md) — shifted form (immediate << 16). - [`addcx`](addcx.md) — XO-form: register operands, sets `XER[CA]`. -- [`subfic`](subfic.md) — D-form: `RT ← SIMM − RA` with `XER[CA]`. +- [`subfic`](subficx.md) — D-form: `RT ← SIMM − RA` with `XER[CA]`. ## IBM Reference diff --git a/tools/ppc-manual/alu/addicx.md b/tools/ppc-manual/alu/addicx.md index 948ef02c..970810a1 100644 --- a/tools/ppc-manual/alu/addicx.md +++ b/tools/ppc-manual/alu/addicx.md @@ -121,7 +121,7 @@ int InstrEmit_addicx(PPCHIRBuilder& f, const InstrData& i) { - [`addic`](addic.md) — same op without the CR0 update. - [`addi`](addi.md), [`addis`](addis.md) — immediate adds without `XER[CA]`. - [`addcx`](addcx.md) — XO-form register equivalent. -- [`subfic`](subfic.md) — `RT ← SIMM − RA` with `XER[CA]` (no record form exists). +- [`subfic`](subficx.md) — `RT ← SIMM − RA` with `XER[CA]` (no record form exists). - [`cmpi`](cmpi.md) — explicit immediate compare when the carry side-effect would be unwanted. ## IBM Reference diff --git a/tools/ppc-manual/alu/cmp.md b/tools/ppc-manual/alu/cmp.md index 46152d88..c6c56b88 100644 --- a/tools/ppc-manual/alu/cmp.md +++ b/tools/ppc-manual/alu/cmp.md @@ -150,7 +150,7 @@ CR[BF] <- { LT: a s b, EQ: a = b, SO: XER[SO] } ; signed - [`cmpi`](cmpi.md) — signed compare against a 16-bit immediate. - [`cmpl`](cmpl.md), [`cmpli`](cmpli.md) — unsigned versions. - [`cmpw`](cmp.md), [`cmpd`](cmp.md) — simplified mnemonics selecting `L`. -- [`mcrxr`](mcrxr.md) — move `XER[SO..CA]` into a CR field and clear them; used to reset sticky overflow. +- [`mcrxr`](../control/mcrxr.md) — move `XER[SO..CA]` into a CR field and clear them; used to reset sticky overflow. - Every `Rc=1` ALU instruction ([`addx`](addx.md), [`subfx`](subfx.md), [`andx`](andx.md), …) — these implicitly perform a signed-compare-to-zero into `cr0`; use explicit `cmp` only when comparing two non-zero values or using a non-zero CR field. ## IBM Reference diff --git a/tools/ppc-manual/alu/cmpi.md b/tools/ppc-manual/alu/cmpi.md index 01ff14ff..29fce100 100644 --- a/tools/ppc-manual/alu/cmpi.md +++ b/tools/ppc-manual/alu/cmpi.md @@ -136,7 +136,7 @@ int InstrEmit_cmpi(PPCHIRBuilder& f, const InstrData& i) { - [`cmpli`](cmpli.md) — unsigned compare against immediate (zero-extended). - [`cmpl`](cmpl.md) — unsigned register compare. - `cmpwi`, `cmpdi` (simplified mnemonics) — select `L=0` / `L=1`. -- [`mcrxr`](mcrxr.md) — clear sticky overflow before a fresh compare sequence. +- [`mcrxr`](../control/mcrxr.md) — clear sticky overflow before a fresh compare sequence. ## IBM Reference diff --git a/tools/ppc-manual/alu/cmpl.md b/tools/ppc-manual/alu/cmpl.md index aec4690b..d3b95fd4 100644 --- a/tools/ppc-manual/alu/cmpl.md +++ b/tools/ppc-manual/alu/cmpl.md @@ -139,7 +139,7 @@ int InstrEmit_cmpl(PPCHIRBuilder& f, const InstrData& i) { - [`cmpli`](cmpli.md) — unsigned compare against a 16-bit immediate. - [`cmpi`](cmpi.md) — signed immediate compare. - `cmplw`, `cmpld` (simplified) — preferred forms in disassembly. -- [`mcrxr`](mcrxr.md) — clear sticky overflow. +- [`mcrxr`](../control/mcrxr.md) — clear sticky overflow. ## IBM Reference diff --git a/tools/ppc-manual/alu/divdx.md b/tools/ppc-manual/alu/divdx.md index 556fd58b..3adff40f 100644 --- a/tools/ppc-manual/alu/divdx.md +++ b/tools/ppc-manual/alu/divdx.md @@ -125,7 +125,7 @@ int InstrEmit_divdx(PPCHIRBuilder& f, const InstrData& i) { ## Special Cases & Edge Conditions - **Two undefined-behaviour cases.** Division by zero (`RB == 0`) and signed-min divided by negative-one (`RA == INT64_MIN && RB == -1`, which would mathematically produce `2^63`, unrepresentable in `i64`). PowerISA leaves `RT` *boundedly undefined* in both cases. Canary's emitter checks neither; its x64 backend skips the divide in both and yields `RT = 0`, so a translator matching Canary returns 0. -- **No exception raised.** Xenon does not trap on either undefined case; the consuming code is expected to have validated `RB` first, e.g. with `cmpdi`/`bne`. If you need a trap, follow the divide with [`tw`](../control/tw.md)/`twi` (these live outside the ALU page set). +- **No exception raised.** Xenon does not trap on either undefined case; the consuming code is expected to have validated `RB` first, e.g. with `cmpdi`/`bne`. If you need a trap, follow the divide with [`tw`](../branch/tw.md)/`twi` (these live outside the ALU page set). - **`OE=1` should set `XER[OV]`** for both undefined cases plus any operand triggering overflow; Canary's `OE` branch is `XEINSTRNOTIMPLEMENTED()`. - **`Rc=1` CR0 update is 32-bit in Canary, as elsewhere.** `f.UpdateCR(0, v)` truncates the 64-bit quotient to `INT32` before the compare; spec compares all 64 bits. - **Latency.** Integer divide is the slowest ALU instruction on Xenon — 70+ cycles, non-pipelined. Hot inner loops avoid it via reciprocal-multiply or shift; expect to see `mulhwu`-based reciprocals in optimised disassembly. diff --git a/tools/ppc-manual/alu/subfx.md b/tools/ppc-manual/alu/subfx.md index 7cde3140..4b010eea 100644 --- a/tools/ppc-manual/alu/subfx.md +++ b/tools/ppc-manual/alu/subfx.md @@ -137,7 +137,7 @@ if Rc then - [`subfcx`](subfcx.md) — subtract-from producing `XER[CA]` (borrow-out). - [`subfex`](subfex.md) — `~RA + RB + XER[CA]` (subtract-with-borrow chain). - [`subfmex`](subfmex.md), [`subfzex`](subfzex.md) — subtract-from `−1` / `0` with carry-in (propagates borrows). -- [`subfic`](subfic.md) — D-form: `RT ← SIMM − RA` with `XER[CA]`. +- [`subfic`](subficx.md) — D-form: `RT ← SIMM − RA` with `XER[CA]`. - [`negx`](negx.md) — specialises to `0 − RA`. - [`addx`](addx.md) — inverse; shares overflow machinery. diff --git a/tools/ppc-manual/branch/tdi.md b/tools/ppc-manual/branch/tdi.md index 1575f50e..0a938411 100644 --- a/tools/ppc-manual/branch/tdi.md +++ b/tools/ppc-manual/branch/tdi.md @@ -124,7 +124,7 @@ int InstrEmit_tdi(PPCHIRBuilder& f, const InstrData& i) { - [`td`](td.md) — register-register doubleword trap (X-form). - [`twi`](twi.md) / [`tw`](tw.md) — 32-bit-comparison siblings. - [`sc`](sc.md) — kernel-entry counterpart via system call exception. -- [`mtmsrd`](mtmsrd.md) (control category) — kernel `rfid`-style return path after handling. +- [`mtmsrd`](../control/mtmsrd.md) (control category) — kernel `rfid`-style return path after handling. ### Simplified Mnemonics diff --git a/tools/ppc-manual/categories/alu.md b/tools/ppc-manual/categories/alu.md index e730e3b7..6fc34f85 100644 --- a/tools/ppc-manual/categories/alu.md +++ b/tools/ppc-manual/categories/alu.md @@ -8,75 +8,75 @@ Fixed-point add/sub/multiply/divide, logical, rotate, shift, compare, count-lead | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`addcx`](addcx.md) | `XO` | Add Carrying | `addcx` | -| [`addex`](addex.md) | `XO` | Add Extended | `addex` | -| [`addi`](addi.md) | `D` | Add Immediate | `addi` | -| [`addic`](addic.md) | `D` | Add Immediate Carrying | `addic` | -| [`addic.`](addicx.md) | `D` | Add Immediate Carrying and Record | `addic.` | -| [`addis`](addis.md) | `D` | Add Immediate Shifted | `addis` | -| [`addmex`](addmex.md) | `XO` | Add to Minus One Extended | `addmex` | -| [`addx`](addx.md) | `XO` | Add | `addx` | -| [`addzex`](addzex.md) | `XO` | Add to Zero Extended | `addzex` | -| [`andcx`](andcx.md) | `X` | AND with Complement | `andcx` | -| [`andi.`](andix.md) | `D` | AND Immediate | `andi.` | -| [`andis.`](andisx.md) | `D` | AND Immediate Shifted | `andis.` | -| [`andx`](andx.md) | `X` | AND | `andx` | -| [`cmp`](cmp.md) | `X` | Compare | `cmp` | -| [`cmpi`](cmpi.md) | `D` | Compare Immediate | `cmpi` | -| [`cmpl`](cmpl.md) | `X` | Compare Logical | `cmpl` | -| [`cmpli`](cmpli.md) | `D` | Compare Logical Immediate | `cmpli` | -| [`cntlzdx`](cntlzdx.md) | `X` | Count Leading Zeros Doubleword | `cntlzdx` | -| [`cntlzwx`](cntlzwx.md) | `X` | Count Leading Zeros Word | `cntlzwx` | -| [`divdux`](divdux.md) | `XO` | Divide Doubleword Unsigned | `divdux` | -| [`divdx`](divdx.md) | `XO` | Divide Doubleword | `divdx` | -| [`divwux`](divwux.md) | `XO` | Divide Word Unsigned | `divwux` | -| [`divwx`](divwx.md) | `XO` | Divide Word | `divwx` | -| [`eieio`](eieio.md) | `X` | Enforce In-Order Execution of I/O | `eieio` | -| [`eqvx`](eqvx.md) | `X` | Equivalent | `eqvx` | -| [`extsbx`](extsbx.md) | `X` | Extend Sign Byte | `extsbx` | -| [`extshx`](extshx.md) | `X` | Extend Sign Half Word | `extshx` | -| [`extswx`](extswx.md) | `X` | Extend Sign Word | `extswx` | -| [`isync`](isync.md) | `XL` | Instruction Synchronize | `isync` | -| [`mulhdux`](mulhdux.md) | `XO` | Multiply High Doubleword Unsigned | `mulhdux` | -| [`mulhdx`](mulhdx.md) | `XO` | Multiply High Doubleword | `mulhdx` | -| [`mulhwux`](mulhwux.md) | `XO` | Multiply High Word Unsigned | `mulhwux` | -| [`mulhwx`](mulhwx.md) | `XO` | Multiply High Word | `mulhwx` | -| [`mulldx`](mulldx.md) | `XO` | Multiply Low Doubleword | `mulldx` | -| [`mulli`](mulli.md) | `D` | Multiply Low Immediate | `mulli` | -| [`mullwx`](mullwx.md) | `XO` | Multiply Low Word | `mullwx` | -| [`nandx`](nandx.md) | `X` | NAND | `nandx` | -| [`negx`](negx.md) | `XO` | Negate | `negx` | -| [`norx`](norx.md) | `X` | NOR | `norx` | -| [`orcx`](orcx.md) | `X` | OR with Complement | `orcx` | -| [`ori`](ori.md) | `D` | OR Immediate | `ori` | -| [`oris`](oris.md) | `D` | OR Immediate Shifted | `oris` | -| [`orx`](orx.md) | `X` | OR | `orx` | -| [`rldclx`](rldclx.md) | `MDS` | Rotate Left Doubleword then Clear Left | `rldclx` | -| [`rldcrx`](rldcrx.md) | `MDS` | Rotate Left Doubleword then Clear Right | `rldcrx` | -| [`rldiclx`](rldiclx.md) | `MD` | Rotate Left Doubleword Immediate then Clear Left | `rldiclx` | -| [`rldicrx`](rldicrx.md) | `MD` | Rotate Left Doubleword Immediate then Clear Right | `rldicrx` | -| [`rldicx`](rldicx.md) | `MD` | Rotate Left Doubleword Immediate then Clear | `rldicx` | -| [`rldimix`](rldimix.md) | `MD` | Rotate Left Doubleword Immediate then Mask Insert | `rldimix` | -| [`rlwimix`](rlwimix.md) | `M` | Rotate Left Word Immediate then Mask Insert | `rlwimix` | -| [`rlwinmx`](rlwinmx.md) | `M` | Rotate Left Word Immediate then AND with Mask | `rlwinmx` | -| [`rlwnmx`](rlwnmx.md) | `M` | Rotate Left Word then AND with Mask | `rlwnmx` | -| [`sldx`](sldx.md) | `X` | Shift Left Doubleword | `sldx` | -| [`slwx`](slwx.md) | `X` | Shift Left Word | `slwx` | -| [`sradix`](sradix.md) | `XS` | Shift Right Algebraic Doubleword Immediate | `sradix` | -| [`sradx`](sradx.md) | `X` | Shift Right Algebraic Doubleword | `sradx` | -| [`srawix`](srawix.md) | `X` | Shift Right Algebraic Word Immediate | `srawix` | -| [`srawx`](srawx.md) | `X` | Shift Right Algebraic Word | `srawx` | -| [`srdx`](srdx.md) | `X` | Shift Right Doubleword | `srdx` | -| [`srwx`](srwx.md) | `X` | Shift Right Word | `srwx` | -| [`subfcx`](subfcx.md) | `XO` | Subtract From Carrying | `subfcx` | -| [`subfex`](subfex.md) | `XO` | Subtract From Extended | `subfex` | -| [`subficx`](subficx.md) | `D` | Subtract From Immediate Carrying | `subficx` | -| [`subfmex`](subfmex.md) | `XO` | Subtract From Minus One Extended | `subfmex` | -| [`subfx`](subfx.md) | `XO` | Subtract From | `subfx` | -| [`subfzex`](subfzex.md) | `XO` | Subtract From Zero Extended | `subfzex` | -| [`sync`](sync.md) | `X` | Synchronize | `sync` | -| [`xori`](xori.md) | `D` | XOR Immediate | `xori` | -| [`xoris`](xoris.md) | `D` | XOR Immediate Shifted | `xoris` | -| [`xorx`](xorx.md) | `X` | XOR | `xorx` | +| [`addcx`](../alu/addcx.md) | `XO` | Add Carrying | `addcx` | +| [`addex`](../alu/addex.md) | `XO` | Add Extended | `addex` | +| [`addi`](../alu/addi.md) | `D` | Add Immediate | `addi` | +| [`addic`](../alu/addic.md) | `D` | Add Immediate Carrying | `addic` | +| [`addic.`](../alu/addicx.md) | `D` | Add Immediate Carrying and Record | `addic.` | +| [`addis`](../alu/addis.md) | `D` | Add Immediate Shifted | `addis` | +| [`addmex`](../alu/addmex.md) | `XO` | Add to Minus One Extended | `addmex` | +| [`addx`](../alu/addx.md) | `XO` | Add | `addx` | +| [`addzex`](../alu/addzex.md) | `XO` | Add to Zero Extended | `addzex` | +| [`andcx`](../alu/andcx.md) | `X` | AND with Complement | `andcx` | +| [`andi.`](../alu/andix.md) | `D` | AND Immediate | `andi.` | +| [`andis.`](../alu/andisx.md) | `D` | AND Immediate Shifted | `andis.` | +| [`andx`](../alu/andx.md) | `X` | AND | `andx` | +| [`cmp`](../alu/cmp.md) | `X` | Compare | `cmp` | +| [`cmpi`](../alu/cmpi.md) | `D` | Compare Immediate | `cmpi` | +| [`cmpl`](../alu/cmpl.md) | `X` | Compare Logical | `cmpl` | +| [`cmpli`](../alu/cmpli.md) | `D` | Compare Logical Immediate | `cmpli` | +| [`cntlzdx`](../alu/cntlzdx.md) | `X` | Count Leading Zeros Doubleword | `cntlzdx` | +| [`cntlzwx`](../alu/cntlzwx.md) | `X` | Count Leading Zeros Word | `cntlzwx` | +| [`divdux`](../alu/divdux.md) | `XO` | Divide Doubleword Unsigned | `divdux` | +| [`divdx`](../alu/divdx.md) | `XO` | Divide Doubleword | `divdx` | +| [`divwux`](../alu/divwux.md) | `XO` | Divide Word Unsigned | `divwux` | +| [`divwx`](../alu/divwx.md) | `XO` | Divide Word | `divwx` | +| [`eieio`](../alu/eieio.md) | `X` | Enforce In-Order Execution of I/O | `eieio` | +| [`eqvx`](../alu/eqvx.md) | `X` | Equivalent | `eqvx` | +| [`extsbx`](../alu/extsbx.md) | `X` | Extend Sign Byte | `extsbx` | +| [`extshx`](../alu/extshx.md) | `X` | Extend Sign Half Word | `extshx` | +| [`extswx`](../alu/extswx.md) | `X` | Extend Sign Word | `extswx` | +| [`isync`](../alu/isync.md) | `XL` | Instruction Synchronize | `isync` | +| [`mulhdux`](../alu/mulhdux.md) | `XO` | Multiply High Doubleword Unsigned | `mulhdux` | +| [`mulhdx`](../alu/mulhdx.md) | `XO` | Multiply High Doubleword | `mulhdx` | +| [`mulhwux`](../alu/mulhwux.md) | `XO` | Multiply High Word Unsigned | `mulhwux` | +| [`mulhwx`](../alu/mulhwx.md) | `XO` | Multiply High Word | `mulhwx` | +| [`mulldx`](../alu/mulldx.md) | `XO` | Multiply Low Doubleword | `mulldx` | +| [`mulli`](../alu/mulli.md) | `D` | Multiply Low Immediate | `mulli` | +| [`mullwx`](../alu/mullwx.md) | `XO` | Multiply Low Word | `mullwx` | +| [`nandx`](../alu/nandx.md) | `X` | NAND | `nandx` | +| [`negx`](../alu/negx.md) | `XO` | Negate | `negx` | +| [`norx`](../alu/norx.md) | `X` | NOR | `norx` | +| [`orcx`](../alu/orcx.md) | `X` | OR with Complement | `orcx` | +| [`ori`](../alu/ori.md) | `D` | OR Immediate | `ori` | +| [`oris`](../alu/oris.md) | `D` | OR Immediate Shifted | `oris` | +| [`orx`](../alu/orx.md) | `X` | OR | `orx` | +| [`rldclx`](../alu/rldclx.md) | `MDS` | Rotate Left Doubleword then Clear Left | `rldclx` | +| [`rldcrx`](../alu/rldcrx.md) | `MDS` | Rotate Left Doubleword then Clear Right | `rldcrx` | +| [`rldiclx`](../alu/rldiclx.md) | `MD` | Rotate Left Doubleword Immediate then Clear Left | `rldiclx` | +| [`rldicrx`](../alu/rldicrx.md) | `MD` | Rotate Left Doubleword Immediate then Clear Right | `rldicrx` | +| [`rldicx`](../alu/rldicx.md) | `MD` | Rotate Left Doubleword Immediate then Clear | `rldicx` | +| [`rldimix`](../alu/rldimix.md) | `MD` | Rotate Left Doubleword Immediate then Mask Insert | `rldimix` | +| [`rlwimix`](../alu/rlwimix.md) | `M` | Rotate Left Word Immediate then Mask Insert | `rlwimix` | +| [`rlwinmx`](../alu/rlwinmx.md) | `M` | Rotate Left Word Immediate then AND with Mask | `rlwinmx` | +| [`rlwnmx`](../alu/rlwnmx.md) | `M` | Rotate Left Word then AND with Mask | `rlwnmx` | +| [`sldx`](../alu/sldx.md) | `X` | Shift Left Doubleword | `sldx` | +| [`slwx`](../alu/slwx.md) | `X` | Shift Left Word | `slwx` | +| [`sradix`](../alu/sradix.md) | `XS` | Shift Right Algebraic Doubleword Immediate | `sradix` | +| [`sradx`](../alu/sradx.md) | `X` | Shift Right Algebraic Doubleword | `sradx` | +| [`srawix`](../alu/srawix.md) | `X` | Shift Right Algebraic Word Immediate | `srawix` | +| [`srawx`](../alu/srawx.md) | `X` | Shift Right Algebraic Word | `srawx` | +| [`srdx`](../alu/srdx.md) | `X` | Shift Right Doubleword | `srdx` | +| [`srwx`](../alu/srwx.md) | `X` | Shift Right Word | `srwx` | +| [`subfcx`](../alu/subfcx.md) | `XO` | Subtract From Carrying | `subfcx` | +| [`subfex`](../alu/subfex.md) | `XO` | Subtract From Extended | `subfex` | +| [`subficx`](../alu/subficx.md) | `D` | Subtract From Immediate Carrying | `subficx` | +| [`subfmex`](../alu/subfmex.md) | `XO` | Subtract From Minus One Extended | `subfmex` | +| [`subfx`](../alu/subfx.md) | `XO` | Subtract From | `subfx` | +| [`subfzex`](../alu/subfzex.md) | `XO` | Subtract From Zero Extended | `subfzex` | +| [`sync`](../alu/sync.md) | `X` | Synchronize | `sync` | +| [`xori`](../alu/xori.md) | `D` | XOR Immediate | `xori` | +| [`xoris`](../alu/xoris.md) | `D` | XOR Immediate Shifted | `xoris` | +| [`xorx`](../alu/xorx.md) | `X` | XOR | `xorx` | diff --git a/tools/ppc-manual/categories/branch.md b/tools/ppc-manual/categories/branch.md index 9f2eba12..f437e16c 100644 --- a/tools/ppc-manual/categories/branch.md +++ b/tools/ppc-manual/categories/branch.md @@ -8,14 +8,14 @@ Unconditional / conditional branches, branch to LR/CTR, traps, system call. | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`bcctrx`](bcctrx.md) | `XL` | Branch Conditional to Count Register | `bcctrx` | -| [`bclrx`](bclrx.md) | `XL` | Branch Conditional to Link Register | `bclrx` | -| [`bcx`](bcx.md) | `B` | Branch Conditional | `bcx` | -| [`bx`](bx.md) | `I` | Branch | `bx` | -| [`sc`](sc.md) | `SC` | System Call | `sc` | -| [`td`](td.md) | `X` | Trap Doubleword | `td` | -| [`tdi`](tdi.md) | `D` | Trap Doubleword Immediate | `tdi` | -| [`tw`](tw.md) | `X` | Trap Word | `tw` | -| [`twi`](twi.md) | `D` | Trap Word Immediate | `twi` | +| [`bcctrx`](../branch/bcctrx.md) | `XL` | Branch Conditional to Count Register | `bcctrx` | +| [`bclrx`](../branch/bclrx.md) | `XL` | Branch Conditional to Link Register | `bclrx` | +| [`bcx`](../branch/bcx.md) | `B` | Branch Conditional | `bcx` | +| [`bx`](../branch/bx.md) | `I` | Branch | `bx` | +| [`sc`](../branch/sc.md) | `SC` | System Call | `sc` | +| [`td`](../branch/td.md) | `X` | Trap Doubleword | `td` | +| [`tdi`](../branch/tdi.md) | `D` | Trap Doubleword Immediate | `tdi` | +| [`tw`](../branch/tw.md) | `X` | Trap Word | `tw` | +| [`twi`](../branch/twi.md) | `D` | Trap Word Immediate | `twi` | diff --git a/tools/ppc-manual/categories/control.md b/tools/ppc-manual/categories/control.md index 3f5cf579..853b4e96 100644 --- a/tools/ppc-manual/categories/control.md +++ b/tools/ppc-manual/categories/control.md @@ -8,31 +8,31 @@ Condition-register logical ops, CR field moves, mfspr/mtspr/mtcrf, time-base rea | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`crand`](crand.md) | `XL` | Condition Register AND | `crand` | -| [`crandc`](crandc.md) | `XL` | Condition Register AND with Complement | `crandc` | -| [`creqv`](creqv.md) | `XL` | Condition Register Equivalent | `creqv` | -| [`crnand`](crnand.md) | `XL` | Condition Register NAND | `crnand` | -| [`crnor`](crnor.md) | `XL` | Condition Register NOR | `crnor` | -| [`cror`](cror.md) | `XL` | Condition Register OR | `cror` | -| [`crorc`](crorc.md) | `XL` | Condition Register OR with Complement | `crorc` | -| [`crxor`](crxor.md) | `XL` | Condition Register XOR | `crxor` | -| [`mcrf`](mcrf.md) | `XL` | Move Condition Register Field | `mcrf` | -| [`mcrfs`](mcrfs.md) | `X` | Move to Condition Register from FPSCR | `mcrfs` | -| [`mcrxr`](mcrxr.md) | `X` | Move to Condition Register from XER | `mcrxr` | -| [`mfcr`](mfcr.md) | `X` | Move from Condition Register | `mfcr` | -| [`mffsx`](mffsx.md) | `X` | Move from FPSCR | `mffsx` | -| [`mfmsr`](mfmsr.md) | `X` | Move from Machine State Register | `mfmsr` | -| [`mfspr`](mfspr.md) | `XFX` | Move from Special-Purpose Register | `mfspr` | -| [`mftb`](mftb.md) | `XFX` | Move from Time Base | `mftb` | -| [`mfvscr`](mfvscr.md) | `VX` | Move from VSCR | `mfvscr` | -| [`mtcrf`](mtcrf.md) | `XFX` | Move to Condition Register Fields | `mtcrf` | -| [`mtfsb0x`](mtfsb0x.md) | `X` | Move to FPSCR Bit 0 | `mtfsb0x` | -| [`mtfsb1x`](mtfsb1x.md) | `X` | Move to FPSCR Bit 1 | `mtfsb1x` | -| [`mtfsfix`](mtfsfix.md) | `X` | Move to FPSCR Field Immediate | `mtfsfix` | -| [`mtfsfx`](mtfsfx.md) | `XFL` | Move to FPSCR Fields | `mtfsfx` | -| [`mtmsr`](mtmsr.md) | `X` | Move to Machine State Register | `mtmsr` | -| [`mtmsrd`](mtmsrd.md) | `X` | Move to Machine State Register Doubleword | `mtmsrd` | -| [`mtspr`](mtspr.md) | `XFX` | Move to Special-Purpose Register | `mtspr` | -| [`mtvscr`](mtvscr.md) | `VX` | Move to VSCR | `mtvscr` | +| [`crand`](../control/crand.md) | `XL` | Condition Register AND | `crand` | +| [`crandc`](../control/crandc.md) | `XL` | Condition Register AND with Complement | `crandc` | +| [`creqv`](../control/creqv.md) | `XL` | Condition Register Equivalent | `creqv` | +| [`crnand`](../control/crnand.md) | `XL` | Condition Register NAND | `crnand` | +| [`crnor`](../control/crnor.md) | `XL` | Condition Register NOR | `crnor` | +| [`cror`](../control/cror.md) | `XL` | Condition Register OR | `cror` | +| [`crorc`](../control/crorc.md) | `XL` | Condition Register OR with Complement | `crorc` | +| [`crxor`](../control/crxor.md) | `XL` | Condition Register XOR | `crxor` | +| [`mcrf`](../control/mcrf.md) | `XL` | Move Condition Register Field | `mcrf` | +| [`mcrfs`](../control/mcrfs.md) | `X` | Move to Condition Register from FPSCR | `mcrfs` | +| [`mcrxr`](../control/mcrxr.md) | `X` | Move to Condition Register from XER | `mcrxr` | +| [`mfcr`](../control/mfcr.md) | `X` | Move from Condition Register | `mfcr` | +| [`mffsx`](../control/mffsx.md) | `X` | Move from FPSCR | `mffsx` | +| [`mfmsr`](../control/mfmsr.md) | `X` | Move from Machine State Register | `mfmsr` | +| [`mfspr`](../control/mfspr.md) | `XFX` | Move from Special-Purpose Register | `mfspr` | +| [`mftb`](../control/mftb.md) | `XFX` | Move from Time Base | `mftb` | +| [`mfvscr`](../control/mfvscr.md) | `VX` | Move from VSCR | `mfvscr` | +| [`mtcrf`](../control/mtcrf.md) | `XFX` | Move to Condition Register Fields | `mtcrf` | +| [`mtfsb0x`](../control/mtfsb0x.md) | `X` | Move to FPSCR Bit 0 | `mtfsb0x` | +| [`mtfsb1x`](../control/mtfsb1x.md) | `X` | Move to FPSCR Bit 1 | `mtfsb1x` | +| [`mtfsfix`](../control/mtfsfix.md) | `X` | Move to FPSCR Field Immediate | `mtfsfix` | +| [`mtfsfx`](../control/mtfsfx.md) | `XFL` | Move to FPSCR Fields | `mtfsfx` | +| [`mtmsr`](../control/mtmsr.md) | `X` | Move to Machine State Register | `mtmsr` | +| [`mtmsrd`](../control/mtmsrd.md) | `X` | Move to Machine State Register Doubleword | `mtmsrd` | +| [`mtspr`](../control/mtspr.md) | `XFX` | Move to Special-Purpose Register | `mtspr` | +| [`mtvscr`](../control/mtvscr.md) | `VX` | Move to VSCR | `mtvscr` | diff --git a/tools/ppc-manual/categories/fpu.md b/tools/ppc-manual/categories/fpu.md index 363d9f8c..fd33d41f 100644 --- a/tools/ppc-manual/categories/fpu.md +++ b/tools/ppc-manual/categories/fpu.md @@ -8,38 +8,38 @@ IEEE-754 add/sub/mul/div/sqrt, fused multiply-add, conversions, compares, FPSCR | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`fabsx`](fabsx.md) | `X` | Floating Absolute Value | `fabsx` | -| [`faddsx`](faddsx.md) | `A` | Floating Add Single | `faddsx` | -| [`faddx`](faddx.md) | `A` | Floating Add | `faddx` | -| [`fcfidx`](fcfidx.md) | `X` | Floating Convert From Integer Doubleword | `fcfidx` | -| [`fcmpo`](fcmpo.md) | `X` | Floating Compare Ordered | `fcmpo` | -| [`fcmpu`](fcmpu.md) | `X` | Floating Compare Unordered | `fcmpu` | -| [`fctidx`](fctidx.md) | `X` | Floating Convert to Integer Doubleword | `fctidx` | -| [`fctidzx`](fctidzx.md) | `X` | Floating Convert to Integer Doubleword with Round Toward Zero | `fctidzx` | -| [`fctiwx`](fctiwx.md) | `X` | Floating Convert to Integer Word | `fctiwx` | -| [`fctiwzx`](fctiwzx.md) | `X` | Floating Convert to Integer Word with Round Toward Zero | `fctiwzx` | -| [`fdivsx`](fdivsx.md) | `A` | Floating Divide Single | `fdivsx` | -| [`fdivx`](fdivx.md) | `A` | Floating Divide | `fdivx` | -| [`fmaddsx`](fmaddsx.md) | `A` | Floating Multiply-Add Single | `fmaddsx` | -| [`fmaddx`](fmaddx.md) | `A` | Floating Multiply-Add | `fmaddx` | -| [`fmrx`](fmrx.md) | `X` | Floating Move Register | `fmrx` | -| [`fmsubsx`](fmsubsx.md) | `A` | Floating Multiply-Subtract Single | `fmsubsx` | -| [`fmsubx`](fmsubx.md) | `A` | Floating Multiply-Subtract | `fmsubx` | -| [`fmulsx`](fmulsx.md) | `A` | Floating Multiply Single | `fmulsx` | -| [`fmulx`](fmulx.md) | `A` | Floating Multiply | `fmulx` | -| [`fnabsx`](fnabsx.md) | `X` | Floating Negative Absolute Value | `fnabsx` | -| [`fnegx`](fnegx.md) | `X` | Floating Negate | `fnegx` | -| [`fnmaddsx`](fnmaddsx.md) | `A` | Floating Negative Multiply-Add Single | `fnmaddsx` | -| [`fnmaddx`](fnmaddx.md) | `A` | Floating Negative Multiply-Add | `fnmaddx` | -| [`fnmsubsx`](fnmsubsx.md) | `A` | Floating Negative Multiply-Subtract Single | `fnmsubsx` | -| [`fnmsubx`](fnmsubx.md) | `A` | Floating Negative Multiply-Subtract | `fnmsubx` | -| [`fresx`](fresx.md) | `A` | Floating Reciprocal Estimate Single | `fresx` | -| [`frspx`](frspx.md) | `X` | Floating Round to Single | `frspx` | -| [`frsqrtex`](frsqrtex.md) | `A` | Floating Reciprocal Square Root Estimate | `frsqrtex` | -| [`fselx`](fselx.md) | `A` | Floating Select | `fselx` | -| [`fsqrtsx`](fsqrtsx.md) | `A` | Floating Square Root Single | `fsqrtsx` | -| [`fsqrtx`](fsqrtx.md) | `A` | Floating Square Root | `fsqrtx` | -| [`fsubsx`](fsubsx.md) | `A` | Floating Subtract Single | `fsubsx` | -| [`fsubx`](fsubx.md) | `A` | Floating Subtract | `fsubx` | +| [`fabsx`](../fpu/fabsx.md) | `X` | Floating Absolute Value | `fabsx` | +| [`faddsx`](../fpu/faddsx.md) | `A` | Floating Add Single | `faddsx` | +| [`faddx`](../fpu/faddx.md) | `A` | Floating Add | `faddx` | +| [`fcfidx`](../fpu/fcfidx.md) | `X` | Floating Convert From Integer Doubleword | `fcfidx` | +| [`fcmpo`](../fpu/fcmpo.md) | `X` | Floating Compare Ordered | `fcmpo` | +| [`fcmpu`](../fpu/fcmpu.md) | `X` | Floating Compare Unordered | `fcmpu` | +| [`fctidx`](../fpu/fctidx.md) | `X` | Floating Convert to Integer Doubleword | `fctidx` | +| [`fctidzx`](../fpu/fctidzx.md) | `X` | Floating Convert to Integer Doubleword with Round Toward Zero | `fctidzx` | +| [`fctiwx`](../fpu/fctiwx.md) | `X` | Floating Convert to Integer Word | `fctiwx` | +| [`fctiwzx`](../fpu/fctiwzx.md) | `X` | Floating Convert to Integer Word with Round Toward Zero | `fctiwzx` | +| [`fdivsx`](../fpu/fdivsx.md) | `A` | Floating Divide Single | `fdivsx` | +| [`fdivx`](../fpu/fdivx.md) | `A` | Floating Divide | `fdivx` | +| [`fmaddsx`](../fpu/fmaddsx.md) | `A` | Floating Multiply-Add Single | `fmaddsx` | +| [`fmaddx`](../fpu/fmaddx.md) | `A` | Floating Multiply-Add | `fmaddx` | +| [`fmrx`](../fpu/fmrx.md) | `X` | Floating Move Register | `fmrx` | +| [`fmsubsx`](../fpu/fmsubsx.md) | `A` | Floating Multiply-Subtract Single | `fmsubsx` | +| [`fmsubx`](../fpu/fmsubx.md) | `A` | Floating Multiply-Subtract | `fmsubx` | +| [`fmulsx`](../fpu/fmulsx.md) | `A` | Floating Multiply Single | `fmulsx` | +| [`fmulx`](../fpu/fmulx.md) | `A` | Floating Multiply | `fmulx` | +| [`fnabsx`](../fpu/fnabsx.md) | `X` | Floating Negative Absolute Value | `fnabsx` | +| [`fnegx`](../fpu/fnegx.md) | `X` | Floating Negate | `fnegx` | +| [`fnmaddsx`](../fpu/fnmaddsx.md) | `A` | Floating Negative Multiply-Add Single | `fnmaddsx` | +| [`fnmaddx`](../fpu/fnmaddx.md) | `A` | Floating Negative Multiply-Add | `fnmaddx` | +| [`fnmsubsx`](../fpu/fnmsubsx.md) | `A` | Floating Negative Multiply-Subtract Single | `fnmsubsx` | +| [`fnmsubx`](../fpu/fnmsubx.md) | `A` | Floating Negative Multiply-Subtract | `fnmsubx` | +| [`fresx`](../fpu/fresx.md) | `A` | Floating Reciprocal Estimate Single | `fresx` | +| [`frspx`](../fpu/frspx.md) | `X` | Floating Round to Single | `frspx` | +| [`frsqrtex`](../fpu/frsqrtex.md) | `A` | Floating Reciprocal Square Root Estimate | `frsqrtex` | +| [`fselx`](../fpu/fselx.md) | `A` | Floating Select | `fselx` | +| [`fsqrtsx`](../fpu/fsqrtsx.md) | `A` | Floating Square Root Single | `fsqrtsx` | +| [`fsqrtx`](../fpu/fsqrtx.md) | `A` | Floating Square Root | `fsqrtx` | +| [`fsubsx`](../fpu/fsubsx.md) | `A` | Floating Subtract Single | `fsubsx` | +| [`fsubx`](../fpu/fsubx.md) | `A` | Floating Subtract | `fsubx` | diff --git a/tools/ppc-manual/categories/memory.md b/tools/ppc-manual/categories/memory.md index fb8273ea..7438f323 100644 --- a/tools/ppc-manual/categories/memory.md +++ b/tools/ppc-manual/categories/memory.md @@ -8,61 +8,61 @@ Loads/stores for byte, half, word, doubleword, float, multiple and string; cache | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`dcbf`](dcbf.md) | `X` | Data Cache Block Flush | `dcbf` | -| [`dcbi`](dcbi.md) | `X` | Data Cache Block Invalidate | `dcbi` | -| [`dcbst`](dcbst.md) | `X` | Data Cache Block Store | `dcbst` | -| [`dcbt`](dcbt.md) | `X` | Data Cache Block Touch | `dcbt` | -| [`dcbtst`](dcbtst.md) | `X` | Data Cache Block Touch for Store | `dcbtst` | -| [`dcbz`](dcbz.md) | `DCBZ` | Data Cache Block Clear to Zero | `dcbz`, `dcbz128` | -| [`icbi`](icbi.md) | `X` | Instruction Cache Block Invalidate | `icbi` | -| [`lbz`](lbz.md) | `D` | Load Byte and Zero | `lbz`, `lbzu`, `lbzux`, `lbzx` | -| [`ld`](ld.md) | `DS` | Load Doubleword | `ld`, `ldu`, `ldux`, `ldx` | -| [`ldarx`](ldarx.md) | `X` | Load Doubleword and Reserve Indexed | `ldarx` | -| [`ldbrx`](ldbrx.md) | `X` | Load Doubleword Byte-Reverse Indexed | `ldbrx` | -| [`lfd`](lfd.md) | `D` | Load Floating-Point Double | `lfd`, `lfdu`, `lfdux`, `lfdx` | -| [`lfs`](lfs.md) | `D` | Load Floating-Point Single | `lfs`, `lfsu`, `lfsux`, `lfsx` | -| [`lha`](lha.md) | `D` | Load Half Word Algebraic | `lha`, `lhau`, `lhaux`, `lhax` | -| [`lhbrx`](lhbrx.md) | `X` | Load Half Word Byte-Reverse Indexed | `lhbrx` | -| [`lhz`](lhz.md) | `D` | Load Half Word and Zero | `lhz`, `lhzu`, `lhzux`, `lhzx` | -| [`lmw`](lmw.md) | `D` | Load Multiple Word | `lmw` | -| [`lswi`](lswi.md) | `X` | Load String Word Immediate | `lswi` | -| [`lswx`](lswx.md) | `X` | Load String Word Indexed | `lswx` | -| [`lvebx`](lvebx.md) | `X` | Load Vector Element Byte Indexed | `lvebx` | -| [`lvehx`](lvehx.md) | `X` | Load Vector Element Half Word Indexed | `lvehx` | -| [`lvewx`](lvewx.md) | `X` | Load Vector Element Word Indexed | `lvewx`, `lvewx128` | -| [`lvlx`](lvlx.md) | `X` | Load Vector Left Indexed | `lvlx`, `lvlx128` | -| [`lvlxl`](lvlxl.md) | `X` | Load Vector Left Indexed LRU | `lvlxl`, `lvlxl128` | -| [`lvrx`](lvrx.md) | `X` | Load Vector Right Indexed | `lvrx`, `lvrx128` | -| [`lvrxl`](lvrxl.md) | `X` | Load Vector Right Indexed LRU | `lvrxl`, `lvrxl128` | -| [`lvx`](lvx.md) | `X` | Load Vector Indexed | `lvx`, `lvx128` | -| [`lvxl`](lvxl.md) | `X` | Load Vector Indexed LRU | `lvxl`, `lvxl128` | -| [`lwa`](lwa.md) | `DS` | Load Word Algebraic | `lwa`, `lwaux`, `lwax` | -| [`lwarx`](lwarx.md) | `X` | Load Word and Reserve Indexed | `lwarx` | -| [`lwbrx`](lwbrx.md) | `X` | Load Word Byte-Reverse Indexed | `lwbrx` | -| [`lwz`](lwz.md) | `D` | Load Word and Zero | `lwz`, `lwzu`, `lwzux`, `lwzx` | -| [`stb`](stb.md) | `D` | Store Byte | `stb`, `stbu`, `stbux`, `stbx` | -| [`std`](std.md) | `DS` | Store Doubleword | `std`, `stdu`, `stdux`, `stdx` | -| [`stdbrx`](stdbrx.md) | `X` | Store Doubleword Byte-Reverse Indexed | `stdbrx` | -| [`stdcx`](stdcx.md) | `X` | Store Doubleword Conditional Indexed | `stdcx` | -| [`stfd`](stfd.md) | `D` | Store Floating-Point Double | `stfd`, `stfdu`, `stfdux`, `stfdx` | -| [`stfiwx`](stfiwx.md) | `X` | Store Floating-Point as Integer Word Indexed | `stfiwx` | -| [`stfs`](stfs.md) | `D` | Store Floating-Point Single | `stfs`, `stfsu`, `stfsux`, `stfsx` | -| [`sth`](sth.md) | `D` | Store Half Word | `sth`, `sthu`, `sthux`, `sthx` | -| [`sthbrx`](sthbrx.md) | `X` | Store Half Word Byte-Reverse Indexed | `sthbrx` | -| [`stmw`](stmw.md) | `D` | Store Multiple Word | `stmw` | -| [`stswi`](stswi.md) | `X` | Store String Word Immediate | `stswi` | -| [`stswx`](stswx.md) | `X` | Store String Word Indexed | `stswx` | -| [`stvebx`](stvebx.md) | `X` | Store Vector Element Byte Indexed | `stvebx` | -| [`stvehx`](stvehx.md) | `X` | Store Vector Element Half Word Indexed | `stvehx` | -| [`stvewx`](stvewx.md) | `X` | Store Vector Element Word Indexed | `stvewx`, `stvewx128` | -| [`stvlx`](stvlx.md) | `X` | Store Vector Left Indexed | `stvlx`, `stvlx128` | -| [`stvlxl`](stvlxl.md) | `X` | Store Vector Left Indexed LRU | `stvlxl`, `stvlxl128` | -| [`stvrx`](stvrx.md) | `X` | Store Vector Right Indexed | `stvrx`, `stvrx128` | -| [`stvrxl`](stvrxl.md) | `X` | Store Vector Right Indexed LRU | `stvrxl`, `stvrxl128` | -| [`stvx`](stvx.md) | `X` | Store Vector Indexed | `stvx`, `stvx128` | -| [`stvxl`](stvxl.md) | `X` | Store Vector Indexed LRU | `stvxl`, `stvxl128` | -| [`stw`](stw.md) | `D` | Store Word | `stw`, `stwu`, `stwux`, `stwx` | -| [`stwbrx`](stwbrx.md) | `X` | Store Word Byte-Reverse Indexed | `stwbrx` | -| [`stwcx`](stwcx.md) | `X` | Store Word Conditional Indexed | `stwcx` | +| [`dcbf`](../memory/dcbf.md) | `X` | Data Cache Block Flush | `dcbf` | +| [`dcbi`](../memory/dcbi.md) | `X` | Data Cache Block Invalidate | `dcbi` | +| [`dcbst`](../memory/dcbst.md) | `X` | Data Cache Block Store | `dcbst` | +| [`dcbt`](../memory/dcbt.md) | `X` | Data Cache Block Touch | `dcbt` | +| [`dcbtst`](../memory/dcbtst.md) | `X` | Data Cache Block Touch for Store | `dcbtst` | +| [`dcbz`](../memory/dcbz.md) | `DCBZ` | Data Cache Block Clear to Zero | `dcbz`, `dcbz128` | +| [`icbi`](../memory/icbi.md) | `X` | Instruction Cache Block Invalidate | `icbi` | +| [`lbz`](../memory/lbz.md) | `D` | Load Byte and Zero | `lbz`, `lbzu`, `lbzux`, `lbzx` | +| [`ld`](../memory/ld.md) | `DS` | Load Doubleword | `ld`, `ldu`, `ldux`, `ldx` | +| [`ldarx`](../memory/ldarx.md) | `X` | Load Doubleword and Reserve Indexed | `ldarx` | +| [`ldbrx`](../memory/ldbrx.md) | `X` | Load Doubleword Byte-Reverse Indexed | `ldbrx` | +| [`lfd`](../memory/lfd.md) | `D` | Load Floating-Point Double | `lfd`, `lfdu`, `lfdux`, `lfdx` | +| [`lfs`](../memory/lfs.md) | `D` | Load Floating-Point Single | `lfs`, `lfsu`, `lfsux`, `lfsx` | +| [`lha`](../memory/lha.md) | `D` | Load Half Word Algebraic | `lha`, `lhau`, `lhaux`, `lhax` | +| [`lhbrx`](../memory/lhbrx.md) | `X` | Load Half Word Byte-Reverse Indexed | `lhbrx` | +| [`lhz`](../memory/lhz.md) | `D` | Load Half Word and Zero | `lhz`, `lhzu`, `lhzux`, `lhzx` | +| [`lmw`](../memory/lmw.md) | `D` | Load Multiple Word | `lmw` | +| [`lswi`](../memory/lswi.md) | `X` | Load String Word Immediate | `lswi` | +| [`lswx`](../memory/lswx.md) | `X` | Load String Word Indexed | `lswx` | +| [`lvebx`](../memory/lvebx.md) | `X` | Load Vector Element Byte Indexed | `lvebx` | +| [`lvehx`](../memory/lvehx.md) | `X` | Load Vector Element Half Word Indexed | `lvehx` | +| [`lvewx`](../memory/lvewx.md) | `X` | Load Vector Element Word Indexed | `lvewx`, `lvewx128` | +| [`lvlx`](../memory/lvlx.md) | `X` | Load Vector Left Indexed | `lvlx`, `lvlx128` | +| [`lvlxl`](../memory/lvlxl.md) | `X` | Load Vector Left Indexed LRU | `lvlxl`, `lvlxl128` | +| [`lvrx`](../memory/lvrx.md) | `X` | Load Vector Right Indexed | `lvrx`, `lvrx128` | +| [`lvrxl`](../memory/lvrxl.md) | `X` | Load Vector Right Indexed LRU | `lvrxl`, `lvrxl128` | +| [`lvx`](../memory/lvx.md) | `X` | Load Vector Indexed | `lvx`, `lvx128` | +| [`lvxl`](../memory/lvxl.md) | `X` | Load Vector Indexed LRU | `lvxl`, `lvxl128` | +| [`lwa`](../memory/lwa.md) | `DS` | Load Word Algebraic | `lwa`, `lwaux`, `lwax` | +| [`lwarx`](../memory/lwarx.md) | `X` | Load Word and Reserve Indexed | `lwarx` | +| [`lwbrx`](../memory/lwbrx.md) | `X` | Load Word Byte-Reverse Indexed | `lwbrx` | +| [`lwz`](../memory/lwz.md) | `D` | Load Word and Zero | `lwz`, `lwzu`, `lwzux`, `lwzx` | +| [`stb`](../memory/stb.md) | `D` | Store Byte | `stb`, `stbu`, `stbux`, `stbx` | +| [`std`](../memory/std.md) | `DS` | Store Doubleword | `std`, `stdu`, `stdux`, `stdx` | +| [`stdbrx`](../memory/stdbrx.md) | `X` | Store Doubleword Byte-Reverse Indexed | `stdbrx` | +| [`stdcx`](../memory/stdcx.md) | `X` | Store Doubleword Conditional Indexed | `stdcx` | +| [`stfd`](../memory/stfd.md) | `D` | Store Floating-Point Double | `stfd`, `stfdu`, `stfdux`, `stfdx` | +| [`stfiwx`](../memory/stfiwx.md) | `X` | Store Floating-Point as Integer Word Indexed | `stfiwx` | +| [`stfs`](../memory/stfs.md) | `D` | Store Floating-Point Single | `stfs`, `stfsu`, `stfsux`, `stfsx` | +| [`sth`](../memory/sth.md) | `D` | Store Half Word | `sth`, `sthu`, `sthux`, `sthx` | +| [`sthbrx`](../memory/sthbrx.md) | `X` | Store Half Word Byte-Reverse Indexed | `sthbrx` | +| [`stmw`](../memory/stmw.md) | `D` | Store Multiple Word | `stmw` | +| [`stswi`](../memory/stswi.md) | `X` | Store String Word Immediate | `stswi` | +| [`stswx`](../memory/stswx.md) | `X` | Store String Word Indexed | `stswx` | +| [`stvebx`](../memory/stvebx.md) | `X` | Store Vector Element Byte Indexed | `stvebx` | +| [`stvehx`](../memory/stvehx.md) | `X` | Store Vector Element Half Word Indexed | `stvehx` | +| [`stvewx`](../memory/stvewx.md) | `X` | Store Vector Element Word Indexed | `stvewx`, `stvewx128` | +| [`stvlx`](../memory/stvlx.md) | `X` | Store Vector Left Indexed | `stvlx`, `stvlx128` | +| [`stvlxl`](../memory/stvlxl.md) | `X` | Store Vector Left Indexed LRU | `stvlxl`, `stvlxl128` | +| [`stvrx`](../memory/stvrx.md) | `X` | Store Vector Right Indexed | `stvrx`, `stvrx128` | +| [`stvrxl`](../memory/stvrxl.md) | `X` | Store Vector Right Indexed LRU | `stvrxl`, `stvrxl128` | +| [`stvx`](../memory/stvx.md) | `X` | Store Vector Indexed | `stvx`, `stvx128` | +| [`stvxl`](../memory/stvxl.md) | `X` | Store Vector Indexed LRU | `stvxl`, `stvxl128` | +| [`stw`](../memory/stw.md) | `D` | Store Word | `stw`, `stwu`, `stwux`, `stwx` | +| [`stwbrx`](../memory/stwbrx.md) | `X` | Store Word Byte-Reverse Indexed | `stwbrx` | +| [`stwcx`](../memory/stwcx.md) | `X` | Store Word Conditional Indexed | `stwcx` | diff --git a/tools/ppc-manual/categories/vmx.md b/tools/ppc-manual/categories/vmx.md index 288e9d9c..f317cf45 100644 --- a/tools/ppc-manual/categories/vmx.md +++ b/tools/ppc-manual/categories/vmx.md @@ -8,149 +8,149 @@ | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`lvsl`](lvsl.md) | `X` | Load Vector for Shift Left Indexed | `lvsl`, `lvsl128` | -| [`lvsr`](lvsr.md) | `X` | Load Vector for Shift Right Indexed | `lvsr`, `lvsr128` | -| [`vaddcuw`](vaddcuw.md) | `VX` | Vector Add Carryout Unsigned Word | `vaddcuw` | -| [`vaddfp`](vaddfp.md) | `VX` | Vector Add Floating Point | `vaddfp`, `vaddfp128` | -| [`vaddsbs`](vaddsbs.md) | `VX` | Vector Add Signed Byte Saturate | `vaddsbs` | -| [`vaddshs`](vaddshs.md) | `VX` | Vector Add Signed Half Word Saturate | `vaddshs` | -| [`vaddsws`](vaddsws.md) | `VX` | Vector Add Signed Word Saturate | `vaddsws` | -| [`vaddubm`](vaddubm.md) | `VX` | Vector Add Unsigned Byte Modulo | `vaddubm` | -| [`vaddubs`](vaddubs.md) | `VX` | Vector Add Unsigned Byte Saturate | `vaddubs` | -| [`vadduhm`](vadduhm.md) | `VX` | Vector Add Unsigned Half Word Modulo | `vadduhm` | -| [`vadduhs`](vadduhs.md) | `VX` | Vector Add Unsigned Half Word Saturate | `vadduhs` | -| [`vadduwm`](vadduwm.md) | `VX` | Vector Add Unsigned Word Modulo | `vadduwm` | -| [`vadduws`](vadduws.md) | `VX` | Vector Add Unsigned Word Saturate | `vadduws` | -| [`vand`](vand.md) | `VX` | Vector Logical AND | `vand`, `vand128` | -| [`vandc`](vandc.md) | `VX` | Vector Logical AND with Complement | `vandc`, `vandc128` | -| [`vavgsb`](vavgsb.md) | `VX` | Vector Average Signed Byte | `vavgsb` | -| [`vavgsh`](vavgsh.md) | `VX` | Vector Average Signed Half Word | `vavgsh` | -| [`vavgsw`](vavgsw.md) | `VX` | Vector Average Signed Word | `vavgsw` | -| [`vavgub`](vavgub.md) | `VX` | Vector Average Unsigned Byte | `vavgub` | -| [`vavguh`](vavguh.md) | `VX` | Vector Average Unsigned Half Word | `vavguh` | -| [`vavguw`](vavguw.md) | `VX` | Vector Average Unsigned Word | `vavguw` | -| [`vcfsx`](vcfsx.md) | `VX` | Vector Convert from Signed Fixed-Point Word | `vcfsx` | -| [`vcfux`](vcfux.md) | `VX` | Vector Convert from Unsigned Fixed-Point Word | `vcfux` | -| [`vcmpbfp`](vcmpbfp.md) | `VC` | Vector Compare Bounds Floating Point | `vcmpbfp`, `vcmpbfp128` | -| [`vcmpeqfp`](vcmpeqfp.md) | `VC` | Vector Compare Equal-to Floating Point | `vcmpeqfp`, `vcmpeqfp128` | -| [`vcmpequb`](vcmpequb.md) | `VC` | Vector Compare Equal-to Unsigned Byte | `vcmpequb` | -| [`vcmpequh`](vcmpequh.md) | `VC` | Vector Compare Equal-to Unsigned Half Word | `vcmpequh` | -| [`vcmpequw`](vcmpequw.md) | `VC` | Vector Compare Equal-to Unsigned Word | `vcmpequw`, `vcmpequw128` | -| [`vcmpgefp`](vcmpgefp.md) | `VC` | Vector Compare Greater-Than-or-Equal-to Floating Point | `vcmpgefp`, `vcmpgefp128` | -| [`vcmpgtfp`](vcmpgtfp.md) | `VC` | Vector Compare Greater-Than Floating Point | `vcmpgtfp`, `vcmpgtfp128` | -| [`vcmpgtsb`](vcmpgtsb.md) | `VC` | Vector Compare Greater-Than Signed Byte | `vcmpgtsb` | -| [`vcmpgtsh`](vcmpgtsh.md) | `VC` | Vector Compare Greater-Than Signed Half Word | `vcmpgtsh` | -| [`vcmpgtsw`](vcmpgtsw.md) | `VC` | Vector Compare Greater-Than Signed Word | `vcmpgtsw` | -| [`vcmpgtub`](vcmpgtub.md) | `VC` | Vector Compare Greater-Than Unsigned Byte | `vcmpgtub` | -| [`vcmpgtuh`](vcmpgtuh.md) | `VC` | Vector Compare Greater-Than Unsigned Half Word | `vcmpgtuh` | -| [`vcmpgtuw`](vcmpgtuw.md) | `VC` | Vector Compare Greater-Than Unsigned Word | `vcmpgtuw` | -| [`vctsxs`](vctsxs.md) | `VX` | Vector Convert to Signed Fixed-Point Word Saturate | `vctsxs` | -| [`vctuxs`](vctuxs.md) | `VX` | Vector Convert to Unsigned Fixed-Point Word Saturate | `vctuxs` | -| [`vexptefp`](vexptefp.md) | `VX` | Vector 2 Raised to the Exponent Estimate Floating Point | `vexptefp`, `vexptefp128` | -| [`vlogefp`](vlogefp.md) | `VX` | Vector Log2 Estimate Floating Point | `vlogefp`, `vlogefp128` | -| [`vmaddfp`](vmaddfp.md) | `VA` | Vector Multiply-Add Floating Point | `vmaddfp`, `vmaddfp128` | -| [`vmaxfp`](vmaxfp.md) | `VX` | Vector Maximum Floating Point | `vmaxfp`, `vmaxfp128` | -| [`vmaxsb`](vmaxsb.md) | `VX` | Vector Maximum Signed Byte | `vmaxsb` | -| [`vmaxsh`](vmaxsh.md) | `VX` | Vector Maximum Signed Half Word | `vmaxsh` | -| [`vmaxsw`](vmaxsw.md) | `VX` | Vector Maximum Signed Word | `vmaxsw` | -| [`vmaxub`](vmaxub.md) | `VX` | Vector Maximum Unsigned Byte | `vmaxub` | -| [`vmaxuh`](vmaxuh.md) | `VX` | Vector Maximum Unsigned Half Word | `vmaxuh` | -| [`vmaxuw`](vmaxuw.md) | `VX` | Vector Maximum Unsigned Word | `vmaxuw` | -| [`vmhaddshs`](vmhaddshs.md) | `VA` | Vector Multiply-High and Add Signed Signed Half Word Saturate | `vmhaddshs` | -| [`vmhraddshs`](vmhraddshs.md) | `VA` | Vector Multiply-High Round and Add Signed Signed Half Word Saturate | `vmhraddshs` | -| [`vminfp`](vminfp.md) | `VX` | Vector Minimum Floating Point | `vminfp`, `vminfp128` | -| [`vminsb`](vminsb.md) | `VX` | Vector Minimum Signed Byte | `vminsb` | -| [`vminsh`](vminsh.md) | `VX` | Vector Minimum Signed Half Word | `vminsh` | -| [`vminsw`](vminsw.md) | `VX` | Vector Minimum Signed Word | `vminsw` | -| [`vminub`](vminub.md) | `VX` | Vector Minimum Unsigned Byte | `vminub` | -| [`vminuh`](vminuh.md) | `VX` | Vector Minimum Unsigned Half Word | `vminuh` | -| [`vminuw`](vminuw.md) | `VX` | Vector Minimum Unsigned Word | `vminuw` | -| [`vmladduhm`](vmladduhm.md) | `VA` | Vector Multiply-Low and Add Unsigned Half Word Modulo | `vmladduhm` | -| [`vmrghb`](vmrghb.md) | `VX` | Vector Merge High Byte | `vmrghb` | -| [`vmrghh`](vmrghh.md) | `VX` | Vector Merge High Half Word | `vmrghh` | -| [`vmrghw`](vmrghw.md) | `VX` | Vector Merge High Word | `vmrghw`, `vmrghw128` | -| [`vmrglb`](vmrglb.md) | `VX` | Vector Merge Low Byte | `vmrglb` | -| [`vmrglh`](vmrglh.md) | `VX` | Vector Merge Low Half Word | `vmrglh` | -| [`vmrglw`](vmrglw.md) | `VX` | Vector Merge Low Word | `vmrglw`, `vmrglw128` | -| [`vmsummbm`](vmsummbm.md) | `VA` | Vector Multiply-Sum Mixed-Sign Byte Modulo | `vmsummbm` | -| [`vmsumshm`](vmsumshm.md) | `VA` | Vector Multiply-Sum Signed Half Word Modulo | `vmsumshm` | -| [`vmsumshs`](vmsumshs.md) | `VA` | Vector Multiply-Sum Signed Half Word Saturate | `vmsumshs` | -| [`vmsumubm`](vmsumubm.md) | `VA` | Vector Multiply-Sum Unsigned Byte Modulo | `vmsumubm` | -| [`vmsumuhm`](vmsumuhm.md) | `VA` | Vector Multiply-Sum Unsigned Half Word Modulo | `vmsumuhm` | -| [`vmsumuhs`](vmsumuhs.md) | `VA` | Vector Multiply-Sum Unsigned Half Word Saturate | `vmsumuhs` | -| [`vmulesb`](vmulesb.md) | `VX` | Vector Multiply Even Signed Byte | `vmulesb` | -| [`vmulesh`](vmulesh.md) | `VX` | Vector Multiply Even Signed Half Word | `vmulesh` | -| [`vmuleub`](vmuleub.md) | `VX` | Vector Multiply Even Unsigned Byte | `vmuleub` | -| [`vmuleuh`](vmuleuh.md) | `VX` | Vector Multiply Even Unsigned Half Word | `vmuleuh` | -| [`vmulosb`](vmulosb.md) | `VX` | Vector Multiply Odd Signed Byte | `vmulosb` | -| [`vmulosh`](vmulosh.md) | `VX` | Vector Multiply Odd Signed Half Word | `vmulosh` | -| [`vmuloub`](vmuloub.md) | `VX` | Vector Multiply Odd Unsigned Byte | `vmuloub` | -| [`vmulouh`](vmulouh.md) | `VX` | Vector Multiply Odd Unsigned Half Word | `vmulouh` | -| [`vnmsubfp`](vnmsubfp.md) | `VA` | Vector Negative Multiply-Subtract Floating Point | `vnmsubfp`, `vnmsubfp128` | -| [`vnor`](vnor.md) | `VX` | Vector Logical NOR | `vnor`, `vnor128` | -| [`vor`](vor.md) | `VX` | Vector Logical OR | `vor`, `vor128` | -| [`vperm`](vperm.md) | `VA` | Vector Permute | `vperm`, `vperm128` | -| [`vpkpx`](vpkpx.md) | `VX` | Vector Pack Pixel | `vpkpx` | -| [`vpkshss`](vpkshss.md) | `VX` | Vector Pack Signed Half Word Signed Saturate | `vpkshss`, `vpkshss128` | -| [`vpkshus`](vpkshus.md) | `VX` | Vector Pack Signed Half Word Unsigned Saturate | `vpkshus`, `vpkshus128` | -| [`vpkswss`](vpkswss.md) | `VX` | Vector Pack Signed Word Signed Saturate | `vpkswss`, `vpkswss128` | -| [`vpkswus`](vpkswus.md) | `VX` | Vector Pack Signed Word Unsigned Saturate | `vpkswus`, `vpkswus128` | -| [`vpkuhum`](vpkuhum.md) | `VX` | Vector Pack Unsigned Half Word Unsigned Modulo | `vpkuhum`, `vpkuhum128` | -| [`vpkuhus`](vpkuhus.md) | `VX` | Vector Pack Unsigned Half Word Unsigned Saturate | `vpkuhus`, `vpkuhus128` | -| [`vpkuwum`](vpkuwum.md) | `VX` | Vector Pack Unsigned Word Unsigned Modulo | `vpkuwum`, `vpkuwum128` | -| [`vpkuwus`](vpkuwus.md) | `VX` | Vector Pack Unsigned Word Unsigned Saturate | `vpkuwus`, `vpkuwus128` | -| [`vrefp`](vrefp.md) | `VX` | Vector Reciprocal Estimate Floating Point | `vrefp`, `vrefp128` | -| [`vrfim`](vrfim.md) | `VX` | Vector Round to Floating-Point Integer toward -Infinity | `vrfim`, `vrfim128` | -| [`vrfin`](vrfin.md) | `VX` | Vector Round to Floating-Point Integer Nearest | `vrfin`, `vrfin128` | -| [`vrfip`](vrfip.md) | `VX` | Vector Round to Floating-Point Integer toward +Infinity | `vrfip`, `vrfip128` | -| [`vrfiz`](vrfiz.md) | `VX` | Vector Round to Floating-Point Integer toward Zero | `vrfiz`, `vrfiz128` | -| [`vrlb`](vrlb.md) | `VX` | Vector Rotate Left Integer Byte | `vrlb` | -| [`vrlh`](vrlh.md) | `VX` | Vector Rotate Left Integer Half Word | `vrlh` | -| [`vrlw`](vrlw.md) | `VX` | Vector Rotate Left Integer Word | `vrlw`, `vrlw128` | -| [`vrsqrtefp`](vrsqrtefp.md) | `VX` | Vector Reciprocal Square Root Estimate Floating Point | `vrsqrtefp`, `vrsqrtefp128` | -| [`vsel`](vsel.md) | `VA` | Vector Conditional Select | `vsel`, `vsel128` | -| [`vsl`](vsl.md) | `VX` | Vector Shift Left | `vsl` | -| [`vslb`](vslb.md) | `VX` | Vector Shift Left Integer Byte | `vslb` | -| [`vsldoi`](vsldoi.md) | `VA` | Vector Shift Left Double by Octet Immediate | `vsldoi`, `vsldoi128` | -| [`vslh`](vslh.md) | `VX` | Vector Shift Left Integer Half Word | `vslh` | -| [`vslo`](vslo.md) | `VX` | Vector Shift Left by Octet | `vslo`, `vslo128` | -| [`vslw`](vslw.md) | `VX` | Vector Shift Left Integer Word | `vslw`, `vslw128` | -| [`vspltb`](vspltb.md) | `VX` | Vector Splat Byte | `vspltb` | -| [`vsplth`](vsplth.md) | `VX` | Vector Splat Half Word | `vsplth` | -| [`vspltisb`](vspltisb.md) | `VX` | Vector Splat Immediate Signed Byte | `vspltisb` | -| [`vspltish`](vspltish.md) | `VX` | Vector Splat Immediate Signed Half Word | `vspltish` | -| [`vspltisw`](vspltisw.md) | `VX` | Vector Splat Immediate Signed Word | `vspltisw`, `vspltisw128` | -| [`vspltw`](vspltw.md) | `VX` | Vector Splat Word | `vspltw`, `vspltw128` | -| [`vsr`](vsr.md) | `VX` | Vector Shift Right | `vsr` | -| [`vsrab`](vsrab.md) | `VX` | Vector Shift Right Algebraic Byte | `vsrab` | -| [`vsrah`](vsrah.md) | `VX` | Vector Shift Right Algebraic Half Word | `vsrah` | -| [`vsraw`](vsraw.md) | `VX` | Vector Shift Right Algebraic Word | `vsraw`, `vsraw128` | -| [`vsrb`](vsrb.md) | `VX` | Vector Shift Right Byte | `vsrb` | -| [`vsrh`](vsrh.md) | `VX` | Vector Shift Right Half Word | `vsrh` | -| [`vsro`](vsro.md) | `VX` | Vector Shift Right Octet | `vsro`, `vsro128` | -| [`vsrw`](vsrw.md) | `VX` | Vector Shift Right Word | `vsrw`, `vsrw128` | -| [`vsubcuw`](vsubcuw.md) | `VX` | Vector Subtract Carryout Unsigned Word | `vsubcuw` | -| [`vsubfp`](vsubfp.md) | `VX` | Vector Subtract Floating Point | `vsubfp`, `vsubfp128` | -| [`vsubsbs`](vsubsbs.md) | `VX` | Vector Subtract Signed Byte Saturate | `vsubsbs` | -| [`vsubshs`](vsubshs.md) | `VX` | Vector Subtract Signed Half Word Saturate | `vsubshs` | -| [`vsubsws`](vsubsws.md) | `VX` | Vector Subtract Signed Word Saturate | `vsubsws` | -| [`vsububm`](vsububm.md) | `VX` | Vector Subtract Unsigned Byte Modulo | `vsububm` | -| [`vsububs`](vsububs.md) | `VX` | Vector Subtract Unsigned Byte Saturate | `vsububs` | -| [`vsubuhm`](vsubuhm.md) | `VX` | Vector Subtract Unsigned Half Word Modulo | `vsubuhm` | -| [`vsubuhs`](vsubuhs.md) | `VX` | Vector Subtract Unsigned Half Word Saturate | `vsubuhs` | -| [`vsubuwm`](vsubuwm.md) | `VX` | Vector Subtract Unsigned Word Modulo | `vsubuwm` | -| [`vsubuws`](vsubuws.md) | `VX` | Vector Subtract Unsigned Word Saturate | `vsubuws` | -| [`vsum2sws`](vsum2sws.md) | `VX` | Vector Sum Across Partial (1/2) Signed Word Saturate | `vsum2sws` | -| [`vsum4sbs`](vsum4sbs.md) | `VX` | Vector Sum Across Partial (1/4) Signed Byte Saturate | `vsum4sbs` | -| [`vsum4shs`](vsum4shs.md) | `VX` | Vector Sum Across Partial (1/4) Signed Half Word Saturate | `vsum4shs` | -| [`vsum4ubs`](vsum4ubs.md) | `VX` | Vector Sum Across Partial (1/4) Unsigned Byte Saturate | `vsum4ubs` | -| [`vsumsws`](vsumsws.md) | `VX` | Vector Sum Across Signed Word Saturate | `vsumsws` | -| [`vupkhpx`](vupkhpx.md) | `VX` | Vector Unpack High Pixel | `vupkhpx` | -| [`vupkhsb`](vupkhsb.md) | `VX` | Vector Unpack High Signed Byte | `vupkhsb`, `vupkhsb128` | -| [`vupkhsh`](vupkhsh.md) | `VX` | Vector Unpack High Signed Half Word | `vupkhsh` | -| [`vupklpx`](vupklpx.md) | `VX` | Vector Unpack Low Pixel | `vupklpx` | -| [`vupklsb`](vupklsb.md) | `VX` | Vector Unpack Low Signed Byte | `vupklsb`, `vupklsb128` | -| [`vupklsh`](vupklsh.md) | `VX` | Vector Unpack Low Signed Half Word | `vupklsh` | -| [`vxor`](vxor.md) | `VX` | Vector Logical XOR | `vxor`, `vxor128` | +| [`lvsl`](../vmx/lvsl.md) | `X` | Load Vector for Shift Left Indexed | `lvsl`, `lvsl128` | +| [`lvsr`](../vmx/lvsr.md) | `X` | Load Vector for Shift Right Indexed | `lvsr`, `lvsr128` | +| [`vaddcuw`](../vmx/vaddcuw.md) | `VX` | Vector Add Carryout Unsigned Word | `vaddcuw` | +| [`vaddfp`](../vmx/vaddfp.md) | `VX` | Vector Add Floating Point | `vaddfp`, `vaddfp128` | +| [`vaddsbs`](../vmx/vaddsbs.md) | `VX` | Vector Add Signed Byte Saturate | `vaddsbs` | +| [`vaddshs`](../vmx/vaddshs.md) | `VX` | Vector Add Signed Half Word Saturate | `vaddshs` | +| [`vaddsws`](../vmx/vaddsws.md) | `VX` | Vector Add Signed Word Saturate | `vaddsws` | +| [`vaddubm`](../vmx/vaddubm.md) | `VX` | Vector Add Unsigned Byte Modulo | `vaddubm` | +| [`vaddubs`](../vmx/vaddubs.md) | `VX` | Vector Add Unsigned Byte Saturate | `vaddubs` | +| [`vadduhm`](../vmx/vadduhm.md) | `VX` | Vector Add Unsigned Half Word Modulo | `vadduhm` | +| [`vadduhs`](../vmx/vadduhs.md) | `VX` | Vector Add Unsigned Half Word Saturate | `vadduhs` | +| [`vadduwm`](../vmx/vadduwm.md) | `VX` | Vector Add Unsigned Word Modulo | `vadduwm` | +| [`vadduws`](../vmx/vadduws.md) | `VX` | Vector Add Unsigned Word Saturate | `vadduws` | +| [`vand`](../vmx/vand.md) | `VX` | Vector Logical AND | `vand`, `vand128` | +| [`vandc`](../vmx/vandc.md) | `VX` | Vector Logical AND with Complement | `vandc`, `vandc128` | +| [`vavgsb`](../vmx/vavgsb.md) | `VX` | Vector Average Signed Byte | `vavgsb` | +| [`vavgsh`](../vmx/vavgsh.md) | `VX` | Vector Average Signed Half Word | `vavgsh` | +| [`vavgsw`](../vmx/vavgsw.md) | `VX` | Vector Average Signed Word | `vavgsw` | +| [`vavgub`](../vmx/vavgub.md) | `VX` | Vector Average Unsigned Byte | `vavgub` | +| [`vavguh`](../vmx/vavguh.md) | `VX` | Vector Average Unsigned Half Word | `vavguh` | +| [`vavguw`](../vmx/vavguw.md) | `VX` | Vector Average Unsigned Word | `vavguw` | +| [`vcfsx`](../vmx/vcfsx.md) | `VX` | Vector Convert from Signed Fixed-Point Word | `vcfsx` | +| [`vcfux`](../vmx/vcfux.md) | `VX` | Vector Convert from Unsigned Fixed-Point Word | `vcfux` | +| [`vcmpbfp`](../vmx/vcmpbfp.md) | `VC` | Vector Compare Bounds Floating Point | `vcmpbfp`, `vcmpbfp128` | +| [`vcmpeqfp`](../vmx/vcmpeqfp.md) | `VC` | Vector Compare Equal-to Floating Point | `vcmpeqfp`, `vcmpeqfp128` | +| [`vcmpequb`](../vmx/vcmpequb.md) | `VC` | Vector Compare Equal-to Unsigned Byte | `vcmpequb` | +| [`vcmpequh`](../vmx/vcmpequh.md) | `VC` | Vector Compare Equal-to Unsigned Half Word | `vcmpequh` | +| [`vcmpequw`](../vmx/vcmpequw.md) | `VC` | Vector Compare Equal-to Unsigned Word | `vcmpequw`, `vcmpequw128` | +| [`vcmpgefp`](../vmx/vcmpgefp.md) | `VC` | Vector Compare Greater-Than-or-Equal-to Floating Point | `vcmpgefp`, `vcmpgefp128` | +| [`vcmpgtfp`](../vmx/vcmpgtfp.md) | `VC` | Vector Compare Greater-Than Floating Point | `vcmpgtfp`, `vcmpgtfp128` | +| [`vcmpgtsb`](../vmx/vcmpgtsb.md) | `VC` | Vector Compare Greater-Than Signed Byte | `vcmpgtsb` | +| [`vcmpgtsh`](../vmx/vcmpgtsh.md) | `VC` | Vector Compare Greater-Than Signed Half Word | `vcmpgtsh` | +| [`vcmpgtsw`](../vmx/vcmpgtsw.md) | `VC` | Vector Compare Greater-Than Signed Word | `vcmpgtsw` | +| [`vcmpgtub`](../vmx/vcmpgtub.md) | `VC` | Vector Compare Greater-Than Unsigned Byte | `vcmpgtub` | +| [`vcmpgtuh`](../vmx/vcmpgtuh.md) | `VC` | Vector Compare Greater-Than Unsigned Half Word | `vcmpgtuh` | +| [`vcmpgtuw`](../vmx/vcmpgtuw.md) | `VC` | Vector Compare Greater-Than Unsigned Word | `vcmpgtuw` | +| [`vctsxs`](../vmx/vctsxs.md) | `VX` | Vector Convert to Signed Fixed-Point Word Saturate | `vctsxs` | +| [`vctuxs`](../vmx/vctuxs.md) | `VX` | Vector Convert to Unsigned Fixed-Point Word Saturate | `vctuxs` | +| [`vexptefp`](../vmx/vexptefp.md) | `VX` | Vector 2 Raised to the Exponent Estimate Floating Point | `vexptefp`, `vexptefp128` | +| [`vlogefp`](../vmx/vlogefp.md) | `VX` | Vector Log2 Estimate Floating Point | `vlogefp`, `vlogefp128` | +| [`vmaddfp`](../vmx/vmaddfp.md) | `VA` | Vector Multiply-Add Floating Point | `vmaddfp`, `vmaddfp128` | +| [`vmaxfp`](../vmx/vmaxfp.md) | `VX` | Vector Maximum Floating Point | `vmaxfp`, `vmaxfp128` | +| [`vmaxsb`](../vmx/vmaxsb.md) | `VX` | Vector Maximum Signed Byte | `vmaxsb` | +| [`vmaxsh`](../vmx/vmaxsh.md) | `VX` | Vector Maximum Signed Half Word | `vmaxsh` | +| [`vmaxsw`](../vmx/vmaxsw.md) | `VX` | Vector Maximum Signed Word | `vmaxsw` | +| [`vmaxub`](../vmx/vmaxub.md) | `VX` | Vector Maximum Unsigned Byte | `vmaxub` | +| [`vmaxuh`](../vmx/vmaxuh.md) | `VX` | Vector Maximum Unsigned Half Word | `vmaxuh` | +| [`vmaxuw`](../vmx/vmaxuw.md) | `VX` | Vector Maximum Unsigned Word | `vmaxuw` | +| [`vmhaddshs`](../vmx/vmhaddshs.md) | `VA` | Vector Multiply-High and Add Signed Signed Half Word Saturate | `vmhaddshs` | +| [`vmhraddshs`](../vmx/vmhraddshs.md) | `VA` | Vector Multiply-High Round and Add Signed Signed Half Word Saturate | `vmhraddshs` | +| [`vminfp`](../vmx/vminfp.md) | `VX` | Vector Minimum Floating Point | `vminfp`, `vminfp128` | +| [`vminsb`](../vmx/vminsb.md) | `VX` | Vector Minimum Signed Byte | `vminsb` | +| [`vminsh`](../vmx/vminsh.md) | `VX` | Vector Minimum Signed Half Word | `vminsh` | +| [`vminsw`](../vmx/vminsw.md) | `VX` | Vector Minimum Signed Word | `vminsw` | +| [`vminub`](../vmx/vminub.md) | `VX` | Vector Minimum Unsigned Byte | `vminub` | +| [`vminuh`](../vmx/vminuh.md) | `VX` | Vector Minimum Unsigned Half Word | `vminuh` | +| [`vminuw`](../vmx/vminuw.md) | `VX` | Vector Minimum Unsigned Word | `vminuw` | +| [`vmladduhm`](../vmx/vmladduhm.md) | `VA` | Vector Multiply-Low and Add Unsigned Half Word Modulo | `vmladduhm` | +| [`vmrghb`](../vmx/vmrghb.md) | `VX` | Vector Merge High Byte | `vmrghb` | +| [`vmrghh`](../vmx/vmrghh.md) | `VX` | Vector Merge High Half Word | `vmrghh` | +| [`vmrghw`](../vmx/vmrghw.md) | `VX` | Vector Merge High Word | `vmrghw`, `vmrghw128` | +| [`vmrglb`](../vmx/vmrglb.md) | `VX` | Vector Merge Low Byte | `vmrglb` | +| [`vmrglh`](../vmx/vmrglh.md) | `VX` | Vector Merge Low Half Word | `vmrglh` | +| [`vmrglw`](../vmx/vmrglw.md) | `VX` | Vector Merge Low Word | `vmrglw`, `vmrglw128` | +| [`vmsummbm`](../vmx/vmsummbm.md) | `VA` | Vector Multiply-Sum Mixed-Sign Byte Modulo | `vmsummbm` | +| [`vmsumshm`](../vmx/vmsumshm.md) | `VA` | Vector Multiply-Sum Signed Half Word Modulo | `vmsumshm` | +| [`vmsumshs`](../vmx/vmsumshs.md) | `VA` | Vector Multiply-Sum Signed Half Word Saturate | `vmsumshs` | +| [`vmsumubm`](../vmx/vmsumubm.md) | `VA` | Vector Multiply-Sum Unsigned Byte Modulo | `vmsumubm` | +| [`vmsumuhm`](../vmx/vmsumuhm.md) | `VA` | Vector Multiply-Sum Unsigned Half Word Modulo | `vmsumuhm` | +| [`vmsumuhs`](../vmx/vmsumuhs.md) | `VA` | Vector Multiply-Sum Unsigned Half Word Saturate | `vmsumuhs` | +| [`vmulesb`](../vmx/vmulesb.md) | `VX` | Vector Multiply Even Signed Byte | `vmulesb` | +| [`vmulesh`](../vmx/vmulesh.md) | `VX` | Vector Multiply Even Signed Half Word | `vmulesh` | +| [`vmuleub`](../vmx/vmuleub.md) | `VX` | Vector Multiply Even Unsigned Byte | `vmuleub` | +| [`vmuleuh`](../vmx/vmuleuh.md) | `VX` | Vector Multiply Even Unsigned Half Word | `vmuleuh` | +| [`vmulosb`](../vmx/vmulosb.md) | `VX` | Vector Multiply Odd Signed Byte | `vmulosb` | +| [`vmulosh`](../vmx/vmulosh.md) | `VX` | Vector Multiply Odd Signed Half Word | `vmulosh` | +| [`vmuloub`](../vmx/vmuloub.md) | `VX` | Vector Multiply Odd Unsigned Byte | `vmuloub` | +| [`vmulouh`](../vmx/vmulouh.md) | `VX` | Vector Multiply Odd Unsigned Half Word | `vmulouh` | +| [`vnmsubfp`](../vmx/vnmsubfp.md) | `VA` | Vector Negative Multiply-Subtract Floating Point | `vnmsubfp`, `vnmsubfp128` | +| [`vnor`](../vmx/vnor.md) | `VX` | Vector Logical NOR | `vnor`, `vnor128` | +| [`vor`](../vmx/vor.md) | `VX` | Vector Logical OR | `vor`, `vor128` | +| [`vperm`](../vmx/vperm.md) | `VA` | Vector Permute | `vperm`, `vperm128` | +| [`vpkpx`](../vmx/vpkpx.md) | `VX` | Vector Pack Pixel | `vpkpx` | +| [`vpkshss`](../vmx/vpkshss.md) | `VX` | Vector Pack Signed Half Word Signed Saturate | `vpkshss`, `vpkshss128` | +| [`vpkshus`](../vmx/vpkshus.md) | `VX` | Vector Pack Signed Half Word Unsigned Saturate | `vpkshus`, `vpkshus128` | +| [`vpkswss`](../vmx/vpkswss.md) | `VX` | Vector Pack Signed Word Signed Saturate | `vpkswss`, `vpkswss128` | +| [`vpkswus`](../vmx/vpkswus.md) | `VX` | Vector Pack Signed Word Unsigned Saturate | `vpkswus`, `vpkswus128` | +| [`vpkuhum`](../vmx/vpkuhum.md) | `VX` | Vector Pack Unsigned Half Word Unsigned Modulo | `vpkuhum`, `vpkuhum128` | +| [`vpkuhus`](../vmx/vpkuhus.md) | `VX` | Vector Pack Unsigned Half Word Unsigned Saturate | `vpkuhus`, `vpkuhus128` | +| [`vpkuwum`](../vmx/vpkuwum.md) | `VX` | Vector Pack Unsigned Word Unsigned Modulo | `vpkuwum`, `vpkuwum128` | +| [`vpkuwus`](../vmx/vpkuwus.md) | `VX` | Vector Pack Unsigned Word Unsigned Saturate | `vpkuwus`, `vpkuwus128` | +| [`vrefp`](../vmx/vrefp.md) | `VX` | Vector Reciprocal Estimate Floating Point | `vrefp`, `vrefp128` | +| [`vrfim`](../vmx/vrfim.md) | `VX` | Vector Round to Floating-Point Integer toward -Infinity | `vrfim`, `vrfim128` | +| [`vrfin`](../vmx/vrfin.md) | `VX` | Vector Round to Floating-Point Integer Nearest | `vrfin`, `vrfin128` | +| [`vrfip`](../vmx/vrfip.md) | `VX` | Vector Round to Floating-Point Integer toward +Infinity | `vrfip`, `vrfip128` | +| [`vrfiz`](../vmx/vrfiz.md) | `VX` | Vector Round to Floating-Point Integer toward Zero | `vrfiz`, `vrfiz128` | +| [`vrlb`](../vmx/vrlb.md) | `VX` | Vector Rotate Left Integer Byte | `vrlb` | +| [`vrlh`](../vmx/vrlh.md) | `VX` | Vector Rotate Left Integer Half Word | `vrlh` | +| [`vrlw`](../vmx/vrlw.md) | `VX` | Vector Rotate Left Integer Word | `vrlw`, `vrlw128` | +| [`vrsqrtefp`](../vmx/vrsqrtefp.md) | `VX` | Vector Reciprocal Square Root Estimate Floating Point | `vrsqrtefp`, `vrsqrtefp128` | +| [`vsel`](../vmx/vsel.md) | `VA` | Vector Conditional Select | `vsel`, `vsel128` | +| [`vsl`](../vmx/vsl.md) | `VX` | Vector Shift Left | `vsl` | +| [`vslb`](../vmx/vslb.md) | `VX` | Vector Shift Left Integer Byte | `vslb` | +| [`vsldoi`](../vmx/vsldoi.md) | `VA` | Vector Shift Left Double by Octet Immediate | `vsldoi`, `vsldoi128` | +| [`vslh`](../vmx/vslh.md) | `VX` | Vector Shift Left Integer Half Word | `vslh` | +| [`vslo`](../vmx/vslo.md) | `VX` | Vector Shift Left by Octet | `vslo`, `vslo128` | +| [`vslw`](../vmx/vslw.md) | `VX` | Vector Shift Left Integer Word | `vslw`, `vslw128` | +| [`vspltb`](../vmx/vspltb.md) | `VX` | Vector Splat Byte | `vspltb` | +| [`vsplth`](../vmx/vsplth.md) | `VX` | Vector Splat Half Word | `vsplth` | +| [`vspltisb`](../vmx/vspltisb.md) | `VX` | Vector Splat Immediate Signed Byte | `vspltisb` | +| [`vspltish`](../vmx/vspltish.md) | `VX` | Vector Splat Immediate Signed Half Word | `vspltish` | +| [`vspltisw`](../vmx/vspltisw.md) | `VX` | Vector Splat Immediate Signed Word | `vspltisw`, `vspltisw128` | +| [`vspltw`](../vmx/vspltw.md) | `VX` | Vector Splat Word | `vspltw`, `vspltw128` | +| [`vsr`](../vmx/vsr.md) | `VX` | Vector Shift Right | `vsr` | +| [`vsrab`](../vmx/vsrab.md) | `VX` | Vector Shift Right Algebraic Byte | `vsrab` | +| [`vsrah`](../vmx/vsrah.md) | `VX` | Vector Shift Right Algebraic Half Word | `vsrah` | +| [`vsraw`](../vmx/vsraw.md) | `VX` | Vector Shift Right Algebraic Word | `vsraw`, `vsraw128` | +| [`vsrb`](../vmx/vsrb.md) | `VX` | Vector Shift Right Byte | `vsrb` | +| [`vsrh`](../vmx/vsrh.md) | `VX` | Vector Shift Right Half Word | `vsrh` | +| [`vsro`](../vmx/vsro.md) | `VX` | Vector Shift Right Octet | `vsro`, `vsro128` | +| [`vsrw`](../vmx/vsrw.md) | `VX` | Vector Shift Right Word | `vsrw`, `vsrw128` | +| [`vsubcuw`](../vmx/vsubcuw.md) | `VX` | Vector Subtract Carryout Unsigned Word | `vsubcuw` | +| [`vsubfp`](../vmx/vsubfp.md) | `VX` | Vector Subtract Floating Point | `vsubfp`, `vsubfp128` | +| [`vsubsbs`](../vmx/vsubsbs.md) | `VX` | Vector Subtract Signed Byte Saturate | `vsubsbs` | +| [`vsubshs`](../vmx/vsubshs.md) | `VX` | Vector Subtract Signed Half Word Saturate | `vsubshs` | +| [`vsubsws`](../vmx/vsubsws.md) | `VX` | Vector Subtract Signed Word Saturate | `vsubsws` | +| [`vsububm`](../vmx/vsububm.md) | `VX` | Vector Subtract Unsigned Byte Modulo | `vsububm` | +| [`vsububs`](../vmx/vsububs.md) | `VX` | Vector Subtract Unsigned Byte Saturate | `vsububs` | +| [`vsubuhm`](../vmx/vsubuhm.md) | `VX` | Vector Subtract Unsigned Half Word Modulo | `vsubuhm` | +| [`vsubuhs`](../vmx/vsubuhs.md) | `VX` | Vector Subtract Unsigned Half Word Saturate | `vsubuhs` | +| [`vsubuwm`](../vmx/vsubuwm.md) | `VX` | Vector Subtract Unsigned Word Modulo | `vsubuwm` | +| [`vsubuws`](../vmx/vsubuws.md) | `VX` | Vector Subtract Unsigned Word Saturate | `vsubuws` | +| [`vsum2sws`](../vmx/vsum2sws.md) | `VX` | Vector Sum Across Partial (1/2) Signed Word Saturate | `vsum2sws` | +| [`vsum4sbs`](../vmx/vsum4sbs.md) | `VX` | Vector Sum Across Partial (1/4) Signed Byte Saturate | `vsum4sbs` | +| [`vsum4shs`](../vmx/vsum4shs.md) | `VX` | Vector Sum Across Partial (1/4) Signed Half Word Saturate | `vsum4shs` | +| [`vsum4ubs`](../vmx/vsum4ubs.md) | `VX` | Vector Sum Across Partial (1/4) Unsigned Byte Saturate | `vsum4ubs` | +| [`vsumsws`](../vmx/vsumsws.md) | `VX` | Vector Sum Across Signed Word Saturate | `vsumsws` | +| [`vupkhpx`](../vmx/vupkhpx.md) | `VX` | Vector Unpack High Pixel | `vupkhpx` | +| [`vupkhsb`](../vmx/vupkhsb.md) | `VX` | Vector Unpack High Signed Byte | `vupkhsb`, `vupkhsb128` | +| [`vupkhsh`](../vmx/vupkhsh.md) | `VX` | Vector Unpack High Signed Half Word | `vupkhsh` | +| [`vupklpx`](../vmx/vupklpx.md) | `VX` | Vector Unpack Low Pixel | `vupklpx` | +| [`vupklsb`](../vmx/vupklsb.md) | `VX` | Vector Unpack Low Signed Byte | `vupklsb`, `vupklsb128` | +| [`vupklsh`](../vmx/vupklsh.md) | `VX` | Vector Unpack Low Signed Half Word | `vupklsh` | +| [`vxor`](../vmx/vxor.md) | `VX` | Vector Logical XOR | `vxor`, `vxor128` | diff --git a/tools/ppc-manual/categories/vmx128.md b/tools/ppc-manual/categories/vmx128.md index 9526fa06..232c36fa 100644 --- a/tools/ppc-manual/categories/vmx128.md +++ b/tools/ppc-manual/categories/vmx128.md @@ -8,17 +8,17 @@ Xbox-360-specific Altivec extension that widens the vector register file to 128 | Family | Form | Description | Members | | --- | --- | --- | --- | -| [`vcfpsxws128`](vcfpsxws128.md) | `VX128_3` | Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate | `vcfpsxws128` | -| [`vcfpuxws128`](vcfpuxws128.md) | `VX128_3` | Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate | `vcfpuxws128` | -| [`vcsxwfp128`](vcsxwfp128.md) | `VX128_3` | Vector128 Convert From Signed Fixed-Point Word to Floating-Point | `vcsxwfp128` | -| [`vcuxwfp128`](vcuxwfp128.md) | `VX128_3` | Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point | `vcuxwfp128` | -| [`vmaddcfp128`](vmaddcfp128.md) | `VX128` | Vector128 Multiply Add Floating Point | `vmaddcfp128` | -| [`vmsum3fp128`](vmsum3fp128.md) | `VX128` | Vector128 Multiply Sum 3-way Floating Point | `vmsum3fp128` | -| [`vmsum4fp128`](vmsum4fp128.md) | `VX128` | Vector128 Multiply Sum 4-way Floating-Point | `vmsum4fp128` | -| [`vmulfp128`](vmulfp128.md) | `VX128` | Vector128 Multiply Floating-Point | `vmulfp128` | -| [`vpermwi128`](vpermwi128.md) | `VX128_P` | Vector128 Permutate Word Immediate | `vpermwi128` | -| [`vpkd3d128`](vpkd3d128.md) | `VX128_4` | Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert | `vpkd3d128` | -| [`vrlimi128`](vrlimi128.md) | `VX128_4` | Vector128 Rotate Left Immediate and Mask Insert | `vrlimi128` | -| [`vupkd3d128`](vupkd3d128.md) | `VX128_3` | Vector128 Unpack D3Dtype | `vupkd3d128` | +| [`vcfpsxws128`](../vmx128/vcfpsxws128.md) | `VX128_3` | Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate | `vcfpsxws128` | +| [`vcfpuxws128`](../vmx128/vcfpuxws128.md) | `VX128_3` | Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate | `vcfpuxws128` | +| [`vcsxwfp128`](../vmx128/vcsxwfp128.md) | `VX128_3` | Vector128 Convert From Signed Fixed-Point Word to Floating-Point | `vcsxwfp128` | +| [`vcuxwfp128`](../vmx128/vcuxwfp128.md) | `VX128_3` | Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point | `vcuxwfp128` | +| [`vmaddcfp128`](../vmx128/vmaddcfp128.md) | `VX128` | Vector128 Multiply Add Floating Point | `vmaddcfp128` | +| [`vmsum3fp128`](../vmx128/vmsum3fp128.md) | `VX128` | Vector128 Multiply Sum 3-way Floating Point | `vmsum3fp128` | +| [`vmsum4fp128`](../vmx128/vmsum4fp128.md) | `VX128` | Vector128 Multiply Sum 4-way Floating-Point | `vmsum4fp128` | +| [`vmulfp128`](../vmx128/vmulfp128.md) | `VX128` | Vector128 Multiply Floating-Point | `vmulfp128` | +| [`vpermwi128`](../vmx128/vpermwi128.md) | `VX128_P` | Vector128 Permutate Word Immediate | `vpermwi128` | +| [`vpkd3d128`](../vmx128/vpkd3d128.md) | `VX128_4` | Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert | `vpkd3d128` | +| [`vrlimi128`](../vmx128/vrlimi128.md) | `VX128_4` | Vector128 Rotate Left Immediate and Mask Insert | `vrlimi128` | +| [`vupkd3d128`](../vmx128/vupkd3d128.md) | `VX128_3` | Vector128 Unpack D3Dtype | `vupkd3d128` | diff --git a/tools/ppc-manual/forms/VX128.md b/tools/ppc-manual/forms/VX128.md index e22b37ea..6ca323bc 100644 --- a/tools/ppc-manual/forms/VX128.md +++ b/tools/ppc-manual/forms/VX128.md @@ -22,39 +22,39 @@ | Mnemonic | Opcode | Group | Description | | --- | --- | --- | --- | -| [`vaddfp128`](../vmx128/vaddfp.md) | `0x14000010` | vmx | Vector128 Add Floating Point | -| [`vsubfp128`](../vmx128/vsubfp.md) | `0x14000050` | vmx | Vector128 Subtract Floating Point | +| [`vaddfp128`](../vmx/vaddfp.md) | `0x14000010` | vmx | Vector128 Add Floating Point | +| [`vsubfp128`](../vmx/vsubfp.md) | `0x14000050` | vmx | Vector128 Subtract Floating Point | | [`vmulfp128`](../vmx128/vmulfp128.md) | `0x14000090` | vmx | Vector128 Multiply Floating-Point | -| [`vmaddfp128`](../vmx128/vmaddfp.md) | `0x140000d0` | vmx | Vector128 Multiply Add Floating Point | +| [`vmaddfp128`](../vmx/vmaddfp.md) | `0x140000d0` | vmx | Vector128 Multiply Add Floating Point | | [`vmaddcfp128`](../vmx128/vmaddcfp128.md) | `0x14000110` | vmx | Vector128 Multiply Add Floating Point | -| [`vnmsubfp128`](../vmx128/vnmsubfp.md) | `0x14000150` | vmx | Vector128 Negative Multiply-Subtract Floating Point | +| [`vnmsubfp128`](../vmx/vnmsubfp.md) | `0x14000150` | vmx | Vector128 Negative Multiply-Subtract Floating Point | | [`vmsum3fp128`](../vmx128/vmsum3fp128.md) | `0x14000190` | vmx | Vector128 Multiply Sum 3-way Floating Point | | [`vmsum4fp128`](../vmx128/vmsum4fp128.md) | `0x140001d0` | vmx | Vector128 Multiply Sum 4-way Floating-Point | -| [`vpkshss128`](../vmx128/vpkshss.md) | `0x14000200` | vmx | Vector128 Pack Signed Half Word Signed Saturate | -| [`vand128`](../vmx128/vand.md) | `0x14000210` | vmx | Vector128 Logical AND | -| [`vpkshus128`](../vmx128/vpkshus.md) | `0x14000240` | vmx | Vector128 Pack Signed Half Word Unsigned Saturate | -| [`vandc128`](../vmx128/vandc.md) | `0x14000250` | vmx | Vector128 Logical AND with Complement | -| [`vpkswss128`](../vmx128/vpkswss.md) | `0x14000280` | vmx | Vector128 Pack Signed Word Signed Saturate | -| [`vnor128`](../vmx128/vnor.md) | `0x14000290` | vmx | Vector128 Logical NOR | -| [`vpkswus128`](../vmx128/vpkswus.md) | `0x140002c0` | vmx | Vector128 Pack Signed Word Unsigned Saturate | -| [`vor128`](../vmx128/vor.md) | `0x140002d0` | vmx | Vector128 Logical OR | -| [`vpkuhum128`](../vmx128/vpkuhum.md) | `0x14000300` | vmx | Vector128 Pack Unsigned Half Word Unsigned Modulo | -| [`vxor128`](../vmx128/vxor.md) | `0x14000310` | vmx | Vector128 Logical XOR | -| [`vpkuhus128`](../vmx128/vpkuhus.md) | `0x14000340` | vmx | Vector128 Pack Unsigned Half Word Unsigned Saturate | -| [`vsel128`](../vmx128/vsel.md) | `0x14000350` | vmx | Vector128 Conditional Select | -| [`vpkuwum128`](../vmx128/vpkuwum.md) | `0x14000380` | vmx | Vector128 Pack Unsigned Word Unsigned Modulo | -| [`vslo128`](../vmx128/vslo.md) | `0x14000390` | vmx | Vector128 Shift Left Octet | -| [`vpkuwus128`](../vmx128/vpkuwus.md) | `0x140003c0` | vmx | Vector128 Pack Unsigned Word Unsigned Saturate | -| [`vsro128`](../vmx128/vsro.md) | `0x140003d0` | vmx | Vector128 Shift Right Octet | -| [`vrlw128`](../vmx128/vrlw.md) | `0x18000050` | vmx | Vector128 Rotate Left Word | -| [`vslw128`](../vmx128/vslw.md) | `0x180000d0` | vmx | Vector128 Shift Left Integer Word | -| [`vsraw128`](../vmx128/vsraw.md) | `0x18000150` | vmx | Vector128 Shift Right Arithmetic Word | -| [`vsrw128`](../vmx128/vsrw.md) | `0x180001d0` | vmx | Vector128 Shift Right Word | -| [`vmaxfp128`](../vmx128/vmaxfp.md) | `0x18000280` | vmx | Vector128 Maximum Floating Point | -| [`vminfp128`](../vmx128/vminfp.md) | `0x180002c0` | vmx | Vector128 Minimum Floating Point | -| [`vmrghw128`](../vmx128/vmrghw.md) | `0x18000300` | vmx | Vector128 Merge High Word | -| [`vmrglw128`](../vmx128/vmrglw.md) | `0x18000340` | vmx | Vector128 Merge Low Word | -| [`vupkhsb128`](../vmx128/vupkhsb.md) | `0x18000380` | vmx | Vector128 Unpack High Signed Byte | -| [`vupklsb128`](../vmx128/vupklsb.md) | `0x180003c0` | vmx | Vector128 Unpack Low Signed Byte | +| [`vpkshss128`](../vmx/vpkshss.md) | `0x14000200` | vmx | Vector128 Pack Signed Half Word Signed Saturate | +| [`vand128`](../vmx/vand.md) | `0x14000210` | vmx | Vector128 Logical AND | +| [`vpkshus128`](../vmx/vpkshus.md) | `0x14000240` | vmx | Vector128 Pack Signed Half Word Unsigned Saturate | +| [`vandc128`](../vmx/vandc.md) | `0x14000250` | vmx | Vector128 Logical AND with Complement | +| [`vpkswss128`](../vmx/vpkswss.md) | `0x14000280` | vmx | Vector128 Pack Signed Word Signed Saturate | +| [`vnor128`](../vmx/vnor.md) | `0x14000290` | vmx | Vector128 Logical NOR | +| [`vpkswus128`](../vmx/vpkswus.md) | `0x140002c0` | vmx | Vector128 Pack Signed Word Unsigned Saturate | +| [`vor128`](../vmx/vor.md) | `0x140002d0` | vmx | Vector128 Logical OR | +| [`vpkuhum128`](../vmx/vpkuhum.md) | `0x14000300` | vmx | Vector128 Pack Unsigned Half Word Unsigned Modulo | +| [`vxor128`](../vmx/vxor.md) | `0x14000310` | vmx | Vector128 Logical XOR | +| [`vpkuhus128`](../vmx/vpkuhus.md) | `0x14000340` | vmx | Vector128 Pack Unsigned Half Word Unsigned Saturate | +| [`vsel128`](../vmx/vsel.md) | `0x14000350` | vmx | Vector128 Conditional Select | +| [`vpkuwum128`](../vmx/vpkuwum.md) | `0x14000380` | vmx | Vector128 Pack Unsigned Word Unsigned Modulo | +| [`vslo128`](../vmx/vslo.md) | `0x14000390` | vmx | Vector128 Shift Left Octet | +| [`vpkuwus128`](../vmx/vpkuwus.md) | `0x140003c0` | vmx | Vector128 Pack Unsigned Word Unsigned Saturate | +| [`vsro128`](../vmx/vsro.md) | `0x140003d0` | vmx | Vector128 Shift Right Octet | +| [`vrlw128`](../vmx/vrlw.md) | `0x18000050` | vmx | Vector128 Rotate Left Word | +| [`vslw128`](../vmx/vslw.md) | `0x180000d0` | vmx | Vector128 Shift Left Integer Word | +| [`vsraw128`](../vmx/vsraw.md) | `0x18000150` | vmx | Vector128 Shift Right Arithmetic Word | +| [`vsrw128`](../vmx/vsrw.md) | `0x180001d0` | vmx | Vector128 Shift Right Word | +| [`vmaxfp128`](../vmx/vmaxfp.md) | `0x18000280` | vmx | Vector128 Maximum Floating Point | +| [`vminfp128`](../vmx/vminfp.md) | `0x180002c0` | vmx | Vector128 Minimum Floating Point | +| [`vmrghw128`](../vmx/vmrghw.md) | `0x18000300` | vmx | Vector128 Merge High Word | +| [`vmrglw128`](../vmx/vmrglw.md) | `0x18000340` | vmx | Vector128 Merge Low Word | +| [`vupkhsb128`](../vmx/vupkhsb.md) | `0x18000380` | vmx | Vector128 Unpack High Signed Byte | +| [`vupklsb128`](../vmx/vupklsb.md) | `0x180003c0` | vmx | Vector128 Unpack Low Signed Byte | diff --git a/tools/ppc-manual/forms/VX128_1.md b/tools/ppc-manual/forms/VX128_1.md index b356cf5d..5d581786 100644 --- a/tools/ppc-manual/forms/VX128_1.md +++ b/tools/ppc-manual/forms/VX128_1.md @@ -18,8 +18,8 @@ | Mnemonic | Opcode | Group | Description | | --- | --- | --- | --- | -| [`lvsl128`](../vmx128/lvsl.md) | `0x10000003` | vmx | Load Vector for Shift Left Indexed 128 | -| [`lvsr128`](../vmx128/lvsr.md) | `0x10000043` | vmx | Load Vector for Shift Right Indexed 128 | +| [`lvsl128`](../vmx/lvsl.md) | `0x10000003` | vmx | Load Vector for Shift Left Indexed 128 | +| [`lvsr128`](../vmx/lvsr.md) | `0x10000043` | vmx | Load Vector for Shift Right Indexed 128 | | [`lvewx128`](../memory/lvewx.md) | `0x10000083` | memory | Load Vector Element Word Indexed 128 | | [`lvx128`](../memory/lvx.md) | `0x100000c3` | memory | Load Vector Indexed 128 | | [`stvewx128`](../memory/stvewx.md) | `0x10000183` | memory | Store Vector Element Word Indexed 128 | diff --git a/tools/ppc-manual/forms/VX128_2.md b/tools/ppc-manual/forms/VX128_2.md index 22cfa4b3..ecf644f8 100644 --- a/tools/ppc-manual/forms/VX128_2.md +++ b/tools/ppc-manual/forms/VX128_2.md @@ -20,6 +20,6 @@ | Mnemonic | Opcode | Group | Description | | --- | --- | --- | --- | -| [`vperm128`](../vmx128/vperm.md) | `0x14000000` | vmx | Vector128 Permute | +| [`vperm128`](../vmx/vperm.md) | `0x14000000` | vmx | Vector128 Permute | diff --git a/tools/ppc-manual/forms/VX128_3.md b/tools/ppc-manual/forms/VX128_3.md index 98270d68..7734c3b8 100644 --- a/tools/ppc-manual/forms/VX128_3.md +++ b/tools/ppc-manual/forms/VX128_3.md @@ -22,16 +22,16 @@ | [`vcfpuxws128`](../vmx128/vcfpuxws128.md) | `0x18000270` | vmx | Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate | | [`vcsxwfp128`](../vmx128/vcsxwfp128.md) | `0x180002b0` | vmx | Vector128 Convert From Signed Fixed-Point Word to Floating-Point | | [`vcuxwfp128`](../vmx128/vcuxwfp128.md) | `0x180002f0` | vmx | Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point | -| [`vrfim128`](../vmx128/vrfim.md) | `0x18000330` | vmx | Vector128 Round to Floating-Point Integer toward -Infinity | -| [`vrfin128`](../vmx128/vrfin.md) | `0x18000370` | vmx | Vector128 Round to Floating-Point Integer Nearest | -| [`vrfip128`](../vmx128/vrfip.md) | `0x180003b0` | vmx | Vector128 Round to Floating-Point Integer toward +Infinity | -| [`vrfiz128`](../vmx128/vrfiz.md) | `0x180003f0` | vmx | Vector128 Round to Floating-Point Integer toward Zero | -| [`vrefp128`](../vmx128/vrefp.md) | `0x18000630` | vmx | Vector128 Reciprocal Estimate Floating Point | -| [`vrsqrtefp128`](../vmx128/vrsqrtefp.md) | `0x18000670` | vmx | Vector128 Reciprocal Square Root Estimate Floating Point | -| [`vexptefp128`](../vmx128/vexptefp.md) | `0x180006b0` | vmx | Vector128 Log2 Estimate Floating Point | -| [`vlogefp128`](../vmx128/vlogefp.md) | `0x180006f0` | vmx | Vector128 Log2 Estimate Floating Point | -| [`vspltw128`](../vmx128/vspltw.md) | `0x18000730` | vmx | Vector128 Splat Word | -| [`vspltisw128`](../vmx128/vspltisw.md) | `0x18000770` | vmx | Vector128 Splat Immediate Signed Word | +| [`vrfim128`](../vmx/vrfim.md) | `0x18000330` | vmx | Vector128 Round to Floating-Point Integer toward -Infinity | +| [`vrfin128`](../vmx/vrfin.md) | `0x18000370` | vmx | Vector128 Round to Floating-Point Integer Nearest | +| [`vrfip128`](../vmx/vrfip.md) | `0x180003b0` | vmx | Vector128 Round to Floating-Point Integer toward +Infinity | +| [`vrfiz128`](../vmx/vrfiz.md) | `0x180003f0` | vmx | Vector128 Round to Floating-Point Integer toward Zero | +| [`vrefp128`](../vmx/vrefp.md) | `0x18000630` | vmx | Vector128 Reciprocal Estimate Floating Point | +| [`vrsqrtefp128`](../vmx/vrsqrtefp.md) | `0x18000670` | vmx | Vector128 Reciprocal Square Root Estimate Floating Point | +| [`vexptefp128`](../vmx/vexptefp.md) | `0x180006b0` | vmx | Vector128 Log2 Estimate Floating Point | +| [`vlogefp128`](../vmx/vlogefp.md) | `0x180006f0` | vmx | Vector128 Log2 Estimate Floating Point | +| [`vspltw128`](../vmx/vspltw.md) | `0x18000730` | vmx | Vector128 Splat Word | +| [`vspltisw128`](../vmx/vspltisw.md) | `0x18000770` | vmx | Vector128 Splat Immediate Signed Word | | [`vupkd3d128`](../vmx128/vupkd3d128.md) | `0x180007f0` | vmx | Vector128 Unpack D3Dtype | diff --git a/tools/ppc-manual/forms/VX128_5.md b/tools/ppc-manual/forms/VX128_5.md index 27845bf7..cd71081a 100644 --- a/tools/ppc-manual/forms/VX128_5.md +++ b/tools/ppc-manual/forms/VX128_5.md @@ -20,6 +20,6 @@ | Mnemonic | Opcode | Group | Description | | --- | --- | --- | --- | -| [`vsldoi128`](../vmx128/vsldoi.md) | `0x10000010` | vmx | Vector128 Shift Left Double by Octet Immediate | +| [`vsldoi128`](../vmx/vsldoi.md) | `0x10000010` | vmx | Vector128 Shift Left Double by Octet Immediate | diff --git a/tools/ppc-manual/forms/VX128_R.md b/tools/ppc-manual/forms/VX128_R.md index 18dc2a72..2fd7eb4b 100644 --- a/tools/ppc-manual/forms/VX128_R.md +++ b/tools/ppc-manual/forms/VX128_R.md @@ -21,10 +21,10 @@ | Mnemonic | Opcode | Group | Description | | --- | --- | --- | --- | -| [`vcmpeqfp128`](../vmx128/vcmpeqfp.md) | `0x18000000` | vmx | Vector128 Compare Equal-to Floating Point | -| [`vcmpgefp128`](../vmx128/vcmpgefp.md) | `0x18000080` | vmx | Vector128 Compare Greater-Than-or-Equal-to Floating Point | -| [`vcmpgtfp128`](../vmx128/vcmpgtfp.md) | `0x18000100` | vmx | Vector128 Compare Greater-Than Floating-Point | -| [`vcmpbfp128`](../vmx128/vcmpbfp.md) | `0x18000180` | vmx | Vector128 Compare Bounds Floating Point | -| [`vcmpequw128`](../vmx128/vcmpequw.md) | `0x18000200` | vmx | Vector128 Compare Equal-to Unsigned Word | +| [`vcmpeqfp128`](../vmx/vcmpeqfp.md) | `0x18000000` | vmx | Vector128 Compare Equal-to Floating Point | +| [`vcmpgefp128`](../vmx/vcmpgefp.md) | `0x18000080` | vmx | Vector128 Compare Greater-Than-or-Equal-to Floating Point | +| [`vcmpgtfp128`](../vmx/vcmpgtfp.md) | `0x18000100` | vmx | Vector128 Compare Greater-Than Floating-Point | +| [`vcmpbfp128`](../vmx/vcmpbfp.md) | `0x18000180` | vmx | Vector128 Compare Bounds Floating Point | +| [`vcmpequw128`](../vmx/vcmpequw.md) | `0x18000200` | vmx | Vector128 Compare Equal-to Unsigned Word | diff --git a/tools/ppc-manual/fpu/faddsx.md b/tools/ppc-manual/fpu/faddsx.md index 6f46bbff..753c3ecb 100644 --- a/tools/ppc-manual/fpu/faddsx.md +++ b/tools/ppc-manual/fpu/faddsx.md @@ -121,7 +121,7 @@ int InstrEmit_faddsx(PPCHIRBuilder& f, const InstrData& i) { - [`fsubsx`](fsubsx.md), [`fmulsx`](fmulsx.md), [`fdivsx`](fdivsx.md) — other single-precision arithmetic ops. - [`fmaddsx`](fmaddsx.md), [`fmsubsx`](fmsubsx.md), [`fnmaddsx`](fnmaddsx.md), [`fnmsubsx`](fnmsubsx.md) — fused multiply-add single-precision family (single rounding step). - [`frspx`](frspx.md) — explicit double→single rounding helper; `fadds` is essentially `frsp(fadd)` fused into one rounding. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — read/write FPSCR for rounding-mode and exception control. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — read/write FPSCR for rounding-mode and exception control. ## IBM Reference diff --git a/tools/ppc-manual/fpu/faddx.md b/tools/ppc-manual/fpu/faddx.md index 307b64be..5e037325 100644 --- a/tools/ppc-manual/fpu/faddx.md +++ b/tools/ppc-manual/fpu/faddx.md @@ -131,7 +131,7 @@ if Rc then - [`fsubx`](fsubx.md), [`fsubsx`](fsubsx.md) — double / single subtract. - [`fmulx`](fmulx.md), [`fmulsx`](fmulsx.md) — double / single multiply. - [`fmaddx`](fmaddx.md), [`fmsubx`](fmsubx.md), [`fnmaddx`](fnmaddx.md), [`fnmsubx`](fnmsubx.md) — fused multiply-add family (single-rounding; preferred for dot products). -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — read/write FPSCR. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — read/write FPSCR. ## IBM Reference diff --git a/tools/ppc-manual/fpu/fcfidx.md b/tools/ppc-manual/fpu/fcfidx.md index 5883cafa..8ce5c41e 100644 --- a/tools/ppc-manual/fpu/fcfidx.md +++ b/tools/ppc-manual/fpu/fcfidx.md @@ -124,7 +124,7 @@ int InstrEmit_fcfidx(PPCHIRBuilder& f, const InstrData& i) { - [`fctiwx`](fctiwx.md), [`fctiwzx`](fctiwzx.md) — 32-bit integer conversion variants. - [`frspx`](frspx.md) — round to single precision; commonly chained after `fcfid` to produce a `float`. - `lfd`, `stfd` — load/store doubleword used to move integer values between GPR and FPR via memory. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — control rounding mode used by the conversion. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — control rounding mode used by the conversion. ## IBM Reference diff --git a/tools/ppc-manual/fpu/fcmpo.md b/tools/ppc-manual/fpu/fcmpo.md index 5df9e09c..26f3c728 100644 --- a/tools/ppc-manual/fpu/fcmpo.md +++ b/tools/ppc-manual/fpu/fcmpo.md @@ -160,7 +160,7 @@ int InstrEmit_fcmpx_(PPCHIRBuilder& f, const InstrData& i, bool ordered) { - `mcrf`, `mcrfs`, `mfcr` — fan-out CR fields after compare. - `bc`, `bclr`, `bcctr` — conditional branches consume `LT/GT/EQ/SO`. - [`fselx`](fselx.md) — branch-free alternative for single-key compares. -- [`mcrfs`](mcrfs.md), [`mffsx`](mffsx.md) — move FPSCR/CR. +- [`mcrfs`](../control/mcrfs.md), [`mffsx`](../control/mffsx.md) — move FPSCR/CR. ## IBM Reference diff --git a/tools/ppc-manual/fpu/fcmpu.md b/tools/ppc-manual/fpu/fcmpu.md index 376cea7a..1450eeb5 100644 --- a/tools/ppc-manual/fpu/fcmpu.md +++ b/tools/ppc-manual/fpu/fcmpu.md @@ -158,7 +158,7 @@ int InstrEmit_fcmpx_(PPCHIRBuilder& f, const InstrData& i, bool ordered) { - `mcrf`, `mcrfs`, `mfcr` — copy CR fields, useful after `fcmpu` to fan out the result. - `bc`, `bclr`, `bcctr` — conditional branches consume the CR fields written by `fcmpu`. - [`fselx`](fselx.md) — branch-free alternative when only the sign of `FRA - FRB` is needed. -- [`mcrfs`](mcrfs.md), [`mffsx`](mffsx.md) — move FPSCR data into the CR. +- [`mcrfs`](../control/mcrfs.md), [`mffsx`](../control/mffsx.md) — move FPSCR data into the CR. ## IBM Reference diff --git a/tools/ppc-manual/fpu/fctidx.md b/tools/ppc-manual/fpu/fctidx.md index e0cb0f26..5407ac32 100644 --- a/tools/ppc-manual/fpu/fctidx.md +++ b/tools/ppc-manual/fpu/fctidx.md @@ -140,7 +140,7 @@ int InstrEmit_fctidxx_(PPCHIRBuilder& f, const InstrData& i, - [`fctidzx`](fctidzx.md) — same conversion but always rounds toward zero (truncation). - [`fctiwx`](fctiwx.md), [`fctiwzx`](fctiwzx.md) — 32-bit integer variants (saturate to `i32` range). - [`fcfidx`](fcfidx.md) — inverse direction (`i64` → binary64). -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — control `FPSCR[RN]`. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — control `FPSCR[RN]`. - `stfd`, `stfiwx` — store the integer-bits FPR to memory; `stfiwx` stores only the low 32 bits (use after `fctiwx` / `fctiwzx`). ## IBM Reference diff --git a/tools/ppc-manual/fpu/fctiwzx.md b/tools/ppc-manual/fpu/fctiwzx.md index b11caf7e..abc95849 100644 --- a/tools/ppc-manual/fpu/fctiwzx.md +++ b/tools/ppc-manual/fpu/fctiwzx.md @@ -140,7 +140,7 @@ int InstrEmit_fctiwxx_(PPCHIRBuilder& f, const InstrData& i, - [`fctidx`](fctidx.md), [`fctidzx`](fctidzx.md) — 64-bit integer variants. - [`fcfidx`](fcfidx.md) — inverse direction (i64 → f64); for i32 → f64, sign-extend to i64 first. - `stfiwx` — store low 32 bits of FPR; canonical companion. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — FPSCR control (no effect on `fctiwz` since rounding mode is fixed to truncation). +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR control (no effect on `fctiwz` since rounding mode is fixed to truncation). ## IBM Reference diff --git a/tools/ppc-manual/fpu/fdivx.md b/tools/ppc-manual/fpu/fdivx.md index aa79dae0..b530458a 100644 --- a/tools/ppc-manual/fpu/fdivx.md +++ b/tools/ppc-manual/fpu/fdivx.md @@ -130,7 +130,7 @@ int InstrEmit_fdivx(PPCHIRBuilder& f, const InstrData& i) { - [`fresx`](fresx.md) — reciprocal estimate `~1/FRB`; combined with `fmul`/`fmadd` to implement reciprocal divides. - [`fmulx`](fmulx.md), [`faddx`](faddx.md), [`fsubx`](fsubx.md) — companion arithmetic. - [`fmaddx`](fmaddx.md), [`fnmsubx`](fnmsubx.md) — used in Newton-Raphson refinement steps. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — FPSCR control (rounding mode, exception masks). +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR control (rounding mode, exception masks). ## IBM Reference diff --git a/tools/ppc-manual/fpu/fmrx.md b/tools/ppc-manual/fpu/fmrx.md index a546f609..5f062039 100644 --- a/tools/ppc-manual/fpu/fmrx.md +++ b/tools/ppc-manual/fpu/fmrx.md @@ -114,7 +114,7 @@ int InstrEmit_fmrx(PPCHIRBuilder& f, const InstrData& i) { - [`fabsx`](fabsx.md), [`fnegx`](fnegx.md), [`fnabsx`](fnabsx.md) — sign-bit variants of the move (clear / toggle / set). - [`fselx`](fselx.md) — branch-free select; like a conditional `fmr`. -- [`mffsx`](mffsx.md) — read FPSCR into an FPR; complementary "FPR move" for a control register. +- [`mffsx`](../control/mffsx.md) — read FPSCR into an FPR; complementary "FPR move" for a control register. - `stfd`/`lfd` — memory-mediated FPR transfer (much slower; used for register window spills). ## IBM Reference diff --git a/tools/ppc-manual/fpu/fmulx.md b/tools/ppc-manual/fpu/fmulx.md index 901bd6dc..f6a43dee 100644 --- a/tools/ppc-manual/fpu/fmulx.md +++ b/tools/ppc-manual/fpu/fmulx.md @@ -121,7 +121,7 @@ int InstrEmit_fmulx(PPCHIRBuilder& f, const InstrData& i) { - [`fmaddx`](fmaddx.md), [`fmsubx`](fmsubx.md), [`fnmaddx`](fnmaddx.md), [`fnmsubx`](fnmsubx.md) — fused multiply-add family; share the same `FRA × FRC` core but add/subtract `FRB` with a single rounding step. Prefer fused forms for dot products and polynomial evaluation. - [`faddx`](faddx.md), [`fsubx`](fsubx.md), [`fdivx`](fdivx.md) — sibling double-precision arithmetic. - [`fresx`](fresx.md), [`frsqrtex`](frsqrtex.md) — reciprocal helpers commonly paired with `fmul` for reciprocal divides. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — FPSCR control. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR control. ## IBM Reference diff --git a/tools/ppc-manual/fpu/frspx.md b/tools/ppc-manual/fpu/frspx.md index 43193e2f..ee21a562 100644 --- a/tools/ppc-manual/fpu/frspx.md +++ b/tools/ppc-manual/fpu/frspx.md @@ -125,7 +125,7 @@ int InstrEmit_frspx(PPCHIRBuilder& f, const InstrData& i) { - [`fmaddsx`](fmaddsx.md), [`fmsubsx`](fmsubsx.md), [`fnmaddsx`](fnmaddsx.md), [`fnmsubsx`](fnmsubsx.md) — single-precision fused FMA family. - `stfs` — store single; expects an FPR already rounded to single via `frsp` or via single-precision arithmetic. - [`fcfidx`](fcfidx.md) — `fcfid` + `frsp` is the standard `i64 → float` conversion. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — FPSCR rounding-mode control. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR rounding-mode control. ## IBM Reference diff --git a/tools/ppc-manual/fpu/fsqrtx.md b/tools/ppc-manual/fpu/fsqrtx.md index a4247ab6..fd7f5b2b 100644 --- a/tools/ppc-manual/fpu/fsqrtx.md +++ b/tools/ppc-manual/fpu/fsqrtx.md @@ -121,7 +121,7 @@ int InstrEmit_fsqrtx(PPCHIRBuilder& f, const InstrData& i) { - [`frsqrtex`](frsqrtex.md) — reciprocal-square-root estimate (`~1/sqrt(x)`); preferred for normalize/length operations. - [`fresx`](fresx.md) — reciprocal estimate; pairs with `fsqrt` for `1/sqrt(x)`. - [`fmulx`](fmulx.md), [`fmaddx`](fmaddx.md) — used in Newton-Raphson refinement of `frsqrte` outputs. -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md) — FPSCR control. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR control. ## IBM Reference diff --git a/tools/ppc-manual/fpu/fsubx.md b/tools/ppc-manual/fpu/fsubx.md index 2e98235b..6265a16f 100644 --- a/tools/ppc-manual/fpu/fsubx.md +++ b/tools/ppc-manual/fpu/fsubx.md @@ -120,7 +120,7 @@ int InstrEmit_fsubx(PPCHIRBuilder& f, const InstrData& i) { - [`faddx`](faddx.md), [`faddsx`](faddsx.md) — add counterparts; subtract is implemented as add-with-negated-B on most cores. - [`fnegx`](fnegx.md) — sign flip (the bit-pattern operation behind `−FRB`). - [`fmsubx`](fmsubx.md), [`fnmsubx`](fnmsubx.md) — fused multiply-subtract (single rounding step). -- [`mffsx`](mffsx.md), [`mtfsfx`](mtfsfx.md), [`mtfsb0x`](mtfsb0x.md), [`mtfsb1x`](mtfsb1x.md) — FPSCR control. +- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md), [`mtfsb0x`](../control/mtfsb0x.md), [`mtfsb1x`](../control/mtfsb1x.md) — FPSCR control. ## IBM Reference diff --git a/tools/ppc-manual/generator/generate_manual.py b/tools/ppc-manual/generator/generate_manual.py index 3a36a112..8d9cd568 100644 --- a/tools/ppc-manual/generator/generate_manual.py +++ b/tools/ppc-manual/generator/generate_manual.py @@ -806,7 +806,9 @@ def render_category_page(cat_key: str, families: list[Family]) -> str: for family in sorted(families, key=lambda f: f.head): primary = family.primary members = ", ".join(f"`{m.mnem}`" for m in family.members) - rows.append(f"| [`{family.head}`]({_cxx_slug(family.head)}.md) " + # Category pages live in categories/; a family's page lives in its own + # category directory, so the link has to climb out first. + rows.append(f"| [`{family.head}`](../{family.category}/{_cxx_slug(family.head)}.md) " f"| `{primary.form}` | {primary.desc} | {members} |") body = "\n".join(rows) return ( @@ -822,14 +824,18 @@ def render_form_page(form: str, families: list[Family], insns: list[Instruction] bit_table = render_bit_table(form) rows = ["| Mnemonic | Opcode | Group | Description |", "| --- | --- | --- | --- |"] + family_category = {f.head: f.category for f in families} for m in sorted(members_here, key=lambda i: i.opcode_int): cat = _category_for(m) slug = _cxx_slug(m.mnem) # find the family head for the link head = _family_head(m, {i.mnem for i in insns}) - if head not in {f.head for f in families}: + if head not in family_category: head = m.mnem - link = f"../{cat}/{_cxx_slug(head)}.md" + # Link into the directory of the page that documents the family. A + # VMX128 sibling (`vsldoi128`) is documented on its base family's page + # under vmx/, not under the vmx128/ its own category would suggest. + link = f"../{family_category.get(head, cat)}/{_cxx_slug(head)}.md" rows.append(f"| [`{m.mnem}`]({link}) | `0x{m.opcode_hex}` | {GROUP_NAMES[m.group]} | {m.desc} |") body = "\n".join(rows) title_bits = { diff --git a/tools/ppc-manual/memory/dcbf.md b/tools/ppc-manual/memory/dcbf.md index 7da00627..0b91f75a 100644 --- a/tools/ppc-manual/memory/dcbf.md +++ b/tools/ppc-manual/memory/dcbf.md @@ -111,8 +111,8 @@ int InstrEmit_dcbf(PPCHIRBuilder& f, const InstrData& i) { - **`RA0` semantics.** When `RA = 0`, the base is the literal zero — `dcbf 0, RB` flushes the line containing address `RB`. The instruction has no destination register. - **Canary emits host cache hints only.** It keeps no guest-visible cache model: unless the `disable_prefetch_and_cachecontrol` cvar is set, `dcbf` becomes a host `clflush` over the 128-byte cache line (its comment notes Xenon's 128-byte lines), and guest memory is always coherent on the host. This is correct behaviour for an emulator. - **Unprivileged.** `dcbf` is a problem-state instruction — usable from user code. Storage protection still applies; flushing an unmapped page raises a DSI exception. -- **Pair with `sync`.** Hardware `dcbf` does not by itself impose ordering; software that needs the flushed data visible to other masters (DMA, GPU) issues a [`sync`](sync.md) afterwards. -- **Self-modifying code companion.** When patching code, the recipe is `dcbst` (push dirty data through to memory) → `sync` → [`icbi`](icbi.md) (invalidate I-cache) → [`isync`](isync.md). `dcbf` is the heavier alternative when the writer also wants the line out of D-cache. +- **Pair with `sync`.** Hardware `dcbf` does not by itself impose ordering; software that needs the flushed data visible to other masters (DMA, GPU) issues a [`sync`](../alu/sync.md) afterwards. +- **Self-modifying code companion.** When patching code, the recipe is `dcbst` (push dirty data through to memory) → `sync` → [`icbi`](icbi.md) (invalidate I-cache) → [`isync`](../alu/isync.md). `dcbf` is the heavier alternative when the writer also wants the line out of D-cache. ## Related Instructions @@ -121,7 +121,7 @@ int InstrEmit_dcbf(PPCHIRBuilder& f, const InstrData& i) { - [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — touch hints to bring lines in. - [`dcbz`](dcbz.md), `dcbz128` — allocate-and-zero a line. - [`icbi`](icbi.md) — instruction-cache invalidate, used together for self-modifying code. -- [`sync`](sync.md) — full memory barrier, typically follows `dcbf`. +- [`sync`](../alu/sync.md) — full memory barrier, typically follows `dcbf`. ## IBM Reference diff --git a/tools/ppc-manual/memory/dcbi.md b/tools/ppc-manual/memory/dcbi.md index 065a42d7..d854e6ec 100644 --- a/tools/ppc-manual/memory/dcbi.md +++ b/tools/ppc-manual/memory/dcbi.md @@ -97,7 +97,7 @@ _No condition-register or status-register effects._ - **Cache line size.** Xenon lines are 128 bytes. The low seven bits of `EA` are ignored — the operation targets the cache line that contains `EA`. - **`RA0` semantics.** When `RA = 0`, base is literal zero, so `dcbi 0, RB` invalidates the line containing address `RB`. - **Canary does not implement it.** `dcbi` is in its opcode table but has no emitter, so translating one logs "Unimplemented instr" and, with the default `break_on_unimplemented_instructions`, breaks. -- **Sequencing.** Not synchronising. Pair with [`sync`](sync.md) when invalidation must precede a subsequent load on another thread. +- **Sequencing.** Not synchronising. Pair with [`sync`](../alu/sync.md) when invalidation must precede a subsequent load on another thread. - **Architecturally subsumed by `dcbf` for problem state.** Userspace that wants "this line is no longer valuable" must use [`dcbf`](dcbf.md), accepting the write-back cost. ## Related Instructions @@ -107,7 +107,7 @@ _No condition-register or status-register effects._ - [`dcbz`](dcbz.md), `dcbz128` — allocate-and-zero a line. - [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — prefetch hints. - [`icbi`](icbi.md) — instruction-cache analog (also problem-state, not privileged). -- [`sync`](sync.md), [`isync`](isync.md) — pair with cache-control ops for ordering. +- [`sync`](../alu/sync.md), [`isync`](../alu/isync.md) — pair with cache-control ops for ordering. ## IBM Reference diff --git a/tools/ppc-manual/memory/dcbst.md b/tools/ppc-manual/memory/dcbst.md index 6138e543..2d713beb 100644 --- a/tools/ppc-manual/memory/dcbst.md +++ b/tools/ppc-manual/memory/dcbst.md @@ -108,7 +108,7 @@ int InstrEmit_dcbst(PPCHIRBuilder& f, const InstrData& i) { - **Write-through, no invalidate.** If the addressed line is dirty, it is written back to memory; the line itself remains in the cache (clean afterwards). Lighter than `dcbf` — the cache stays warm. - **Cache line size.** Xenon's line is 128 bytes; the low seven bits of `EA` are ignored. There is no `dcbst128`; the operation is sized to the architectural line. - **`RA0` semantics.** `RA = 0` selects literal zero as base. `dcbst 0, RB` pushes the line containing address `RB` to memory. -- **Self-modifying code stage 1.** The canonical "patch then run" sequence is `stw` (modify) → `dcbst` (push dirty data to memory) → [`sync`](sync.md) → [`icbi`](icbi.md) (invalidate I-cache for the same address) → [`isync`](isync.md). `dcbst` is preferred over `dcbf` here because it leaves the data in D-cache for any subsequent normal reads. +- **Self-modifying code stage 1.** The canonical "patch then run" sequence is `stw` (modify) → `dcbst` (push dirty data to memory) → [`sync`](../alu/sync.md) → [`icbi`](icbi.md) (invalidate I-cache for the same address) → [`isync`](../alu/isync.md). `dcbst` is preferred over `dcbf` here because it leaves the data in D-cache for any subsequent normal reads. - **DMA hand-off.** Used before initiating a GPU or DMA read of a buffer the CPU has just written, to ensure memory holds the latest data. - **Unprivileged.** Available from problem state. - **Canary emits a host hint only.** No cache state is simulated: unless the `disable_prefetch_and_cachecontrol` cvar is set, `dcbst` becomes a host `clflush` over the 128-byte cache line, and memory is already authoritative. @@ -120,7 +120,7 @@ int InstrEmit_dcbst(PPCHIRBuilder& f, const InstrData& i) { - [`dcbz`](dcbz.md), `dcbz128` — allocate-and-zero. - [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — prefetch hints. - [`icbi`](icbi.md) — instruction-cache invalidate, sequenced after `dcbst` in self-modifying-code recipes. -- [`sync`](sync.md), [`isync`](isync.md) — ordering primitives that bracket cache control. +- [`sync`](../alu/sync.md), [`isync`](../alu/isync.md) — ordering primitives that bracket cache control. ## IBM Reference diff --git a/tools/ppc-manual/memory/dcbz.md b/tools/ppc-manual/memory/dcbz.md index bf920334..a2f65f85 100644 --- a/tools/ppc-manual/memory/dcbz.md +++ b/tools/ppc-manual/memory/dcbz.md @@ -171,7 +171,7 @@ int InstrEmit_dcbz128(PPCHIRBuilder& f, const InstrData& i) { - **`RA0` semantics.** `RA = 0` selects literal zero as the base, so `dcbz128 0, RB` zeros the line containing address `RB`. The update form does not exist for cache-control instructions. - **Block-fill idiom.** Compilers and hand-written copy loops pair `dcbz128` with `stvx` / `stw` sequences to avoid the cache-line read-allocate that a cold store would trigger. Skipping the read is the entire point. - **Privilege.** `dcbz` is unprivileged (problem-state); does not require supervisor mode. It can fault on protection or unmapped memory like an ordinary store. -- **Sequencing.** Not synchronising. Pair with [`sync`](sync.md) / [`lwsync`](sync.md) when the zeros must be visible before subsequent loads on another thread. +- **Sequencing.** Not synchronising. Pair with [`sync`](../alu/sync.md) / [`lwsync`](../alu/sync.md) when the zeros must be visible before subsequent loads on another thread. ## Related Instructions diff --git a/tools/ppc-manual/memory/icbi.md b/tools/ppc-manual/memory/icbi.md index 22fb49e1..f6cb5d16 100644 --- a/tools/ppc-manual/memory/icbi.md +++ b/tools/ppc-manual/memory/icbi.md @@ -104,7 +104,7 @@ int InstrEmit_icbi(PPCHIRBuilder& f, const InstrData& i) { ## Special Cases & Edge Conditions - **Self-modifying code primitive.** Removes the line containing `EA` from the instruction cache so a subsequent fetch reads from memory. Required after writing new instructions because the I-cache is not coherent with the D-cache or with main memory. -- **Standard recipe.** The full sequence is: `stw` (write new code) → [`dcbst`](dcbst.md) (push dirty data through D-cache to memory) → [`sync`](sync.md) (wait for memory) → `icbi` (drop stale I-cache line) → [`isync`](isync.md) (drain prefetch / refetch). Skipping any of these can leave the CPU executing stale instructions. +- **Standard recipe.** The full sequence is: `stw` (write new code) → [`dcbst`](dcbst.md) (push dirty data through D-cache to memory) → [`sync`](../alu/sync.md) (wait for memory) → `icbi` (drop stale I-cache line) → [`isync`](../alu/isync.md) (drain prefetch / refetch). Skipping any of these can leave the CPU executing stale instructions. - **Cache line size.** Xenon's I-cache line is 128 bytes; the low seven bits of `EA` are ignored. - **`RA0` semantics.** When `RA = 0`, base is the literal zero. `icbi 0, RB` invalidates the line containing address `RB`. - **Unprivileged.** `icbi` is problem-state, unlike its data-side cousin [`dcbi`](dcbi.md). @@ -116,8 +116,8 @@ int InstrEmit_icbi(PPCHIRBuilder& f, const InstrData& i) { - [`dcbst`](dcbst.md) — D-cache write-back (paired step before `icbi`). - [`dcbf`](dcbf.md), [`dcbi`](dcbi.md) — D-cache push / invalidate. -- [`isync`](isync.md) — instruction-stream barrier (paired step after `icbi`). -- [`sync`](sync.md) — full memory barrier between `dcbst` and `icbi`. +- [`isync`](../alu/isync.md) — instruction-stream barrier (paired step after `icbi`). +- [`sync`](../alu/sync.md) — full memory barrier between `dcbst` and `icbi`. ## IBM Reference diff --git a/tools/ppc-manual/memory/ldarx.md b/tools/ppc-manual/memory/ldarx.md index 2461e991..8587fc8a 100644 --- a/tools/ppc-manual/memory/ldarx.md +++ b/tools/ppc-manual/memory/ldarx.md @@ -134,14 +134,14 @@ int InstrEmit_ldarx(PPCHIRBuilder& f, const InstrData& i) { - **Alignment requirement.** `EA` must be 8-byte aligned. An unaligned `ldarx` raises an alignment exception on hardware. Canary does not check; pass aligned addresses. - **`RA0` semantics.** When `RA = 0`, base is literal zero — `ldarx RT, 0, RB` reads at exact `RB`. Used in synthetic-zero atomic-init idioms, but rare. - **Reservation-loss events.** Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code must treat the `stdcx` failure as a normal retry condition, not as an error. -- **Pair atomically.** Code must be `ldarx ... do work ... stdcx.` with no intervening loads or stores that could be re-ordered. Optionally fence with [`lwsync`](sync.md) inside the loop. The conditional store sets `CR0[EQ]` to report success. +- **Pair atomically.** Code must be `ldarx ... do work ... stdcx.` with no intervening loads or stores that could be re-ordered. Optionally fence with [`lwsync`](../alu/sync.md) inside the loop. The conditional store sets `CR0[EQ]` to report success. ## Related Instructions - [`stdcx`](stdcx.md) — store-conditional doubleword (the matching half of the pair). - [`lwarx`](lwarx.md) / [`stwcx`](stwcx.md) — 32-bit reservation pair. - [`ld`](ld.md), [`ldx`](ld.md) — non-reserving doubleword loads. -- [`sync`](sync.md), [`lwsync`](sync.md) — barriers commonly placed around reservation pairs. +- [`sync`](../alu/sync.md), [`lwsync`](../alu/sync.md) — barriers commonly placed around reservation pairs. ## IBM Reference diff --git a/tools/ppc-manual/memory/lha.md b/tools/ppc-manual/memory/lha.md index 978a1c47..cacbb3e2 100644 --- a/tools/ppc-manual/memory/lha.md +++ b/tools/ppc-manual/memory/lha.md @@ -266,7 +266,7 @@ int InstrEmit_lhax(PPCHIRBuilder& f, const InstrData& i) { ## Related Instructions - [`lhz`](lhz.md), [`lhzu`](lhz.md), [`lhzx`](lhz.md), [`lhzux`](lhz.md) — zero-extending counterparts. -- [`lwa`](lwa.md), [`lwax`](lwa.md), [`lwaux`](lwaux.md) — sign-extending word loads (32→64). +- [`lwa`](lwa.md), [`lwax`](lwa.md), [`lwaux`](lwa.md) — sign-extending word loads (32→64). - [`lbz`](lbz.md) — byte load (no sign-extending byte load exists; use `lbz` + `extsb`). - [`lhbrx`](lhbrx.md) — byte-reversed half-word load (zero-extending). - [`sth`](sth.md), [`sthu`](sth.md), [`sthx`](sth.md), [`sthux`](sth.md) — corresponding stores. diff --git a/tools/ppc-manual/memory/lwarx.md b/tools/ppc-manual/memory/lwarx.md index 6710995d..7b2c452c 100644 --- a/tools/ppc-manual/memory/lwarx.md +++ b/tools/ppc-manual/memory/lwarx.md @@ -136,14 +136,14 @@ int InstrEmit_lwarx(PPCHIRBuilder& f, const InstrData& i) { - **Alignment requirement.** `EA` must be 4-byte aligned. An unaligned `lwarx` raises an alignment exception on hardware; Canary does not check. - **`RA0` semantics.** When `RA = 0`, base is literal zero — `lwarx RT, 0, RB` reads at exact `RB`. - **Reservation-loss events.** Any exception, context switch, or store by another thread to the reserved line clears the reservation. Application code treats `stwcx.` failure (CR0[EQ]=0) as a normal retry condition. -- **Pair atomically.** Code must be `lwarx ... do work ... stwcx.` with no intervening loads/stores that could reorder. Optionally fence with [`lwsync`](sync.md) inside the loop. +- **Pair atomically.** Code must be `lwarx ... do work ... stwcx.` with no intervening loads/stores that could reorder. Optionally fence with [`lwsync`](../alu/sync.md) inside the loop. ## Related Instructions - [`stwcx`](stwcx.md) — store-conditional word (the matching half of the pair). - [`ldarx`](ldarx.md) / [`stdcx`](stdcx.md) — 64-bit reservation pair. - [`lwz`](lwz.md), [`lwzx`](lwz.md) — non-reserving word loads. -- [`sync`](sync.md), [`lwsync`](sync.md), [`isync`](isync.md) — barriers commonly placed around reservation pairs. +- [`sync`](../alu/sync.md), [`lwsync`](../alu/sync.md), [`isync`](../alu/isync.md) — barriers commonly placed around reservation pairs. ## IBM Reference diff --git a/tools/ppc-manual/memory/lwz.md b/tools/ppc-manual/memory/lwz.md index 518a4500..ae728232 100644 --- a/tools/ppc-manual/memory/lwz.md +++ b/tools/ppc-manual/memory/lwz.md @@ -271,19 +271,19 @@ int InstrEmit_lwzx(PPCHIRBuilder& f, const InstrData& i) { ## Special Cases & Edge Conditions - **Big-endian memory.** The Xenon reads memory big-endian. Translating to little-endian hosts requires a byte-swap on the 32-bit read (or calling a `mem_read_u32_be` helper as in the C example). Canary does exactly that: `ByteSwap(LoadOffset(…, INT32))`, zero-extended to 64 bits. -- **Zero-extension to 64 bits.** The result occupies the full 64-bit GPR; the high 32 bits are zero. This is semantically distinct from [`lwa`](lwa.md) / [`lwax`](lwax.md) / [`lwaux`](lwaux.md), which sign-extend. Most Xbox 360 code uses `lwz` for unsigned word loads and for pointer loads (addresses are 32-bit and fit in the low half). +- **Zero-extension to 64 bits.** The result occupies the full 64-bit GPR; the high 32 bits are zero. This is semantically distinct from [`lwa`](lwa.md) / [`lwax`](lwa.md) / [`lwaux`](lwa.md), which sign-extend. Most Xbox 360 code uses `lwz` for unsigned word loads and for pointer loads (addresses are 32-bit and fit in the low half). - **`RA0` (non-update forms).** In `lwz` and `lwzx`, when the encoded `RA = 0` the base is the literal zero, **not** `r0`. This enables absolute-address loads `lwz RT, 0x8000(0)` and is heavily used to read from statically-linked data near the TOC base. - **Update forms require `RA ≠ 0`.** `lwzu` / `lwzux` invoke "RA = 0" as an invalid form; AIX docs say the result is undefined and assemblers will refuse to assemble `lwzu RT, d(0)`. Further, `RA = RT` is also invalid (the "effective address" write and the "loaded value" write would race). Canary implements update forms without these checks; rely on incoming code being well-formed. - **No alignment requirement.** Xenon executes unaligned word loads without a fault (unlike some POWER cores). `MEM(EA, 4)` reads four bytes starting at `EA`, whatever alignment. -- **No ordering guarantee.** These are ordinary cached loads; use [`sync`](sync.md) / [`isync`](isync.md) / [`lwsync`](sync.md) for explicit ordering, or [`lwarx`](lwarx.md) for load-reserve semantics. +- **No ordering guarantee.** These are ordinary cached loads; use [`sync`](../alu/sync.md) / [`isync`](../alu/isync.md) / [`lwsync`](../alu/sync.md) for explicit ordering, or [`lwarx`](lwarx.md) for load-reserve semantics. - **Indexed variant operand order.** `lwzx RT, RA, RB` — `RA` is the base (with `RA0` semantics), `RB` is the offset. The variant without `RA0` is `lwzux`. ## Related Instructions -- [`lwa`](lwa.md), [`lwax`](lwax.md), [`lwaux`](lwaux.md) — load word, sign-extend to 64. +- [`lwa`](lwa.md), [`lwax`](lwa.md), [`lwaux`](lwa.md) — load word, sign-extend to 64. - [`lwbrx`](lwbrx.md) — load word byte-reversed (little-endian word). - [`lwarx`](lwarx.md) — load word and reserve (pair with [`stwcx`](stwcx.md)). -- [`ld`](ld.md), [`ldu`](ldu.md), [`ldx`](ldx.md), [`ldux`](ldux.md) — 64-bit loads. +- [`ld`](ld.md), [`ldu`](ld.md), [`ldx`](ld.md), [`ldux`](ld.md) — 64-bit loads. - [`lhz`](lhz.md), [`lbz`](lbz.md) — half-word / byte zero-extending loads (same family structure). - [`stw`](stw.md) family — the corresponding stores. diff --git a/tools/ppc-manual/memory/stdcx.md b/tools/ppc-manual/memory/stdcx.md index fcbd5000..96ff5d73 100644 --- a/tools/ppc-manual/memory/stdcx.md +++ b/tools/ppc-manual/memory/stdcx.md @@ -147,14 +147,14 @@ int InstrEmit_stdcx(PPCHIRBuilder& f, const InstrData& i) { - **`RA0` semantics.** When `RA = 0`, base is literal zero — `stdcx. RS, 0, RB` writes at exact `RB`. - **CR0[SO] reflects XER[SO].** Like all CR-updating ops, CR0[SO] is copied from `XER[SO]` rather than computed from this instruction. - **Spurious failures permitted.** Hardware may report failure even when no actual conflict occurred (e.g. on context switch). Application code treats failure as a normal retry condition. -- **Pair atomically with [`ldarx`](ldarx.md).** Don't interleave loads/stores between the pair; an [`lwsync`](sync.md) inside the loop body is common. +- **Pair atomically with [`ldarx`](ldarx.md).** Don't interleave loads/stores between the pair; an [`lwsync`](../alu/sync.md) inside the loop body is common. ## Related Instructions - [`ldarx`](ldarx.md) — load-and-reserve doubleword (the matching load). - [`stwcx`](stwcx.md) / [`lwarx`](lwarx.md) — 32-bit reservation pair. - [`std`](std.md), [`stdx`](std.md) — non-conditional doubleword stores. -- [`sync`](sync.md), [`lwsync`](sync.md), [`isync`](isync.md) — barriers used around reservation pairs. +- [`sync`](../alu/sync.md), [`lwsync`](../alu/sync.md), [`isync`](../alu/isync.md) — barriers used around reservation pairs. ## IBM Reference diff --git a/tools/ppc-manual/memory/stwcx.md b/tools/ppc-manual/memory/stwcx.md index 63eb6c18..bd1292fe 100644 --- a/tools/ppc-manual/memory/stwcx.md +++ b/tools/ppc-manual/memory/stwcx.md @@ -149,7 +149,7 @@ int InstrEmit_stwcx(PPCHIRBuilder& f, const InstrData& i) { - **`RA0` semantics.** When `RA = 0`, base is literal zero — `stwcx. RS, 0, RB` writes at exact `RB`. - **CR0[SO] reflects XER[SO].** Like all CR-updating ops, CR0[SO] is copied from `XER[SO]` rather than computed. - **Spurious failures permitted.** Hardware may report failure even when no actual conflict occurred (e.g. on context switch). Application code treats failure as a normal retry condition. -- **Pair atomically with [`lwarx`](lwarx.md).** Don't interleave loads/stores between the pair; an [`lwsync`](sync.md) inside the loop body is common. +- **Pair atomically with [`lwarx`](lwarx.md).** Don't interleave loads/stores between the pair; an [`lwsync`](../alu/sync.md) inside the loop body is common. - **Stores low 32 bits of `RS`.** The high 32 bits of the source GPR are ignored. ## Related Instructions @@ -157,7 +157,7 @@ int InstrEmit_stwcx(PPCHIRBuilder& f, const InstrData& i) { - [`lwarx`](lwarx.md) — load-and-reserve word (the matching load). - [`stdcx`](stdcx.md) / [`ldarx`](ldarx.md) — 64-bit reservation pair. - [`stw`](stw.md), [`stwx`](stw.md) — non-conditional word stores. -- [`sync`](sync.md), [`lwsync`](sync.md), [`isync`](isync.md) — barriers used around reservation pairs. +- [`sync`](../alu/sync.md), [`lwsync`](../alu/sync.md), [`isync`](../alu/isync.md) — barriers used around reservation pairs. ## IBM Reference diff --git a/tools/ppc-manual/vmx/lvsl.md b/tools/ppc-manual/vmx/lvsl.md index 8fb33c45..20f2c474 100644 --- a/tools/ppc-manual/vmx/lvsl.md +++ b/tools/ppc-manual/vmx/lvsl.md @@ -179,7 +179,7 @@ for i in 0..15: - [`lvsr`](lvsr.md) — the mirror: `VD[i] = 16 − sh + i`. - [`vperm`](vperm.md) — consumes the mask to perform arbitrary byte-level permutation across two vectors. -- [`lvx`](lvx.md), [`lvlx`](lvlx.md), [`lvrx`](lvrx.md) — the actual memory loads used alongside the mask. +- [`lvx`](../memory/lvx.md), [`lvlx`](../memory/lvlx.md), [`lvrx`](../memory/lvrx.md) — the actual memory loads used alongside the mask. - [`vsldoi`](vsldoi.md) — static-offset shift-double; when the shift is compile-time known, this is cheaper than the `lvsl`/`vperm` pair. ## IBM Reference diff --git a/tools/ppc-manual/vmx/lvsr.md b/tools/ppc-manual/vmx/lvsr.md index ad6a687f..ba8bb11d 100644 --- a/tools/ppc-manual/vmx/lvsr.md +++ b/tools/ppc-manual/vmx/lvsr.md @@ -178,7 +178,7 @@ int InstrEmit_lvsr_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd, - [`lvsl`](lvsl.md) — the mirror: `VD[i] = sh + i`. - [`vperm`](vperm.md) — consumes the mask to perform arbitrary byte-level permutation across two vectors. -- [`lvx`](lvx.md), [`lvlx`](lvlx.md), [`lvrx`](lvrx.md) — the actual memory loads that supply the two aligned halves. +- [`lvx`](../memory/lvx.md), [`lvlx`](../memory/lvlx.md), [`lvrx`](../memory/lvrx.md) — the actual memory loads that supply the two aligned halves. - [`vsldoi`](vsldoi.md) — when the misalignment is a compile-time constant, the static-offset shift is cheaper than the `lvsr`/`vperm` pair. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vaddsbs.md b/tools/ppc-manual/vmx/vaddsbs.md index b0288537..e80ca0c7 100644 --- a/tools/ppc-manual/vmx/vaddsbs.md +++ b/tools/ppc-manual/vmx/vaddsbs.md @@ -120,7 +120,7 @@ int InstrEmit_vaddsbs(PPCHIRBuilder& f, const InstrData& i) { - [`vaddubm`](vaddubm.md) — same width, modulo (non-saturating) add; sign-agnostic. - [`vaddshs`](vaddshs.md), [`vaddsws`](vaddsws.md) — signed saturating add at half / word width. - [`vsubsbs`](vsubsbs.md) — the matching signed saturating subtract. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit observed here. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit observed here. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vaddshs.md b/tools/ppc-manual/vmx/vaddshs.md index 59a7f0e4..59a503f2 100644 --- a/tools/ppc-manual/vmx/vaddshs.md +++ b/tools/ppc-manual/vmx/vaddshs.md @@ -121,7 +121,7 @@ int InstrEmit_vaddshs(PPCHIRBuilder& f, const InstrData& i) { - [`vaddsbs`](vaddsbs.md), [`vaddsws`](vaddsws.md) — signed saturating add at byte / word width. - [`vsubshs`](vsubshs.md) — the matching signed saturating subtract. - [`vmhaddshs`](vmhaddshs.md), [`vmhraddshs`](vmhraddshs.md) — signed-half multiply-add with saturation, common for fixed-point DSP. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear the `VSCR[SAT]` bit affected here. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the `VSCR[SAT]` bit affected here. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vaddsws.md b/tools/ppc-manual/vmx/vaddsws.md index 2a18ea7c..def80df4 100644 --- a/tools/ppc-manual/vmx/vaddsws.md +++ b/tools/ppc-manual/vmx/vaddsws.md @@ -122,7 +122,7 @@ int InstrEmit_vaddsws(PPCHIRBuilder& f, const InstrData& i) { - [`vaddsbs`](vaddsbs.md), [`vaddshs`](vaddshs.md) — signed saturating add at byte / half width. - [`vsubsws`](vsubsws.md) — the matching signed saturating subtract. - [`vmsumshs`](vmsumshs.md), [`vmsumuhs`](vmsumuhs.md) — saturating multiply-sum that often feeds a `vaddsws` chain. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear the `VSCR[SAT]` bit. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the `VSCR[SAT]` bit. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vaddubs.md b/tools/ppc-manual/vmx/vaddubs.md index 89c48495..3b37f435 100644 --- a/tools/ppc-manual/vmx/vaddubs.md +++ b/tools/ppc-manual/vmx/vaddubs.md @@ -121,7 +121,7 @@ int InstrEmit_vaddubs(PPCHIRBuilder& f, const InstrData& i) { - [`vadduhs`](vadduhs.md), [`vadduws`](vadduws.md) — unsigned saturating add at half / word width. - [`vsububs`](vsububs.md) — the matching unsigned saturating subtract (clamps to `0`). - [`vavgub`](vavgub.md) — rounding average; alternative when you want `(a + b + 1) >> 1` without overflow worry. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vadduhs.md b/tools/ppc-manual/vmx/vadduhs.md index d84b05be..0b8adcae 100644 --- a/tools/ppc-manual/vmx/vadduhs.md +++ b/tools/ppc-manual/vmx/vadduhs.md @@ -120,7 +120,7 @@ int InstrEmit_vadduhs(PPCHIRBuilder& f, const InstrData& i) { - [`vaddshs`](vaddshs.md) — same width, signed saturating add (range `-32768..+32767`). - [`vaddubs`](vaddubs.md), [`vadduws`](vadduws.md) — unsigned saturating add at byte / word width. - [`vsubuhs`](vsubuhs.md) — the matching unsigned saturating subtract. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vadduws.md b/tools/ppc-manual/vmx/vadduws.md index 034f3f7b..08eec1e7 100644 --- a/tools/ppc-manual/vmx/vadduws.md +++ b/tools/ppc-manual/vmx/vadduws.md @@ -121,7 +121,7 @@ int InstrEmit_vadduws(PPCHIRBuilder& f, const InstrData& i) { - [`vaddubs`](vaddubs.md), [`vadduhs`](vadduhs.md) — unsigned saturating add at byte / half width. - [`vsubuws`](vsubuws.md) — the matching unsigned saturating subtract. - [`vaddcuw`](vaddcuw.md) — explicit carry-out (paired with the modulo form). -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear the sticky `VSCR[SAT]` bit. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vctsxs.md b/tools/ppc-manual/vmx/vctsxs.md index d1bb37c2..34b10fe7 100644 --- a/tools/ppc-manual/vmx/vctsxs.md +++ b/tools/ppc-manual/vmx/vctsxs.md @@ -118,7 +118,7 @@ int InstrEmit_vctsxs_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb, - **Convert IEEE float lane to signed-Q `int32`, saturating.** For each of the four word lanes, `VD[i] = clamp(round_toward_zero(VB[i] * 2^UIMM), INT32_MIN, INT32_MAX)`. The 5-bit `UIMM` (bits 11..15) gives the Q-format fractional shift, in `0..31`. - **Saturating, not wrapping.** Out-of-range floats clamp to `INT32_MIN` (negative overflow) or `INT32_MAX` (positive overflow) — *not* the wrap-around behaviour of x86 `cvttps2dq` (which produces `0x80000000` on overflow regardless of sign). Canary converts with `vcvttps2dq` and then blends `INT32_MAX` into lanes that overflowed from a non-negative input. - **NaN → 0 in Canary.** It masks NaN lanes to `0` (`vcmpunordps` + `vpandn`). Some references state "NaN → INT32_MIN" for hardware; which one Xenon does is unverified. Canary never records `VSCR[SAT]`. -- **`VSCR[SAT]` is sticky-set** if any lane saturates (overflow or NaN). Cleared only by [`mtvscr`](mtvscr.md). +- **`VSCR[SAT]` is sticky-set** if any lane saturates (overflow or NaN). Cleared only by [`mtvscr`](../control/mtvscr.md). - **Rounding is truncate-toward-zero.** Always; no per-instruction rounding control. - **`VSCR[NJ]` flushes denormal *inputs* to zero before scaling** (Xenon default). - **Big-endian word lanes.** Lane 0 is the most-significant word. @@ -131,7 +131,7 @@ int InstrEmit_vctsxs_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb, - [`vctuxs`](vctuxs.md) — same shape, unsigned destination. - [`vcfsx`](vcfsx.md), [`vcfux`](vcfux.md) — inverse direction (int → float with Q-shift). - [`vrfin`](vrfin.md), [`vrfip`](vrfip.md), [`vrfim`](vrfim.md), [`vrfiz`](vrfiz.md) — float-to-float rounding modes (round-to-nearest, up, down, toward-zero) when staying in float. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear `VSCR[SAT]`. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear `VSCR[SAT]`. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vctuxs.md b/tools/ppc-manual/vmx/vctuxs.md index 92607ab7..73afe44f 100644 --- a/tools/ppc-manual/vmx/vctuxs.md +++ b/tools/ppc-manual/vmx/vctuxs.md @@ -117,7 +117,7 @@ int InstrEmit_vctuxs_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb, - **Convert IEEE float lane to unsigned-Q `uint32`, saturating.** For each of the four word lanes, `VD[i] = clamp(round_toward_zero(VB[i] * 2^UIMM), 0, UINT32_MAX)`. The 5-bit `UIMM` (bits 11..15) gives the Q-format fractional shift, in `0..31`. - **Saturating, not wrapping.** Negative inputs clamp to `0`; values above `2^32 − 1` clamp to `0xFFFF_FFFF`. NaN → `0`. All clamping events sticky-set `VSCR[SAT]` on hardware. Canary reproduces the values — `vmaxps` against zero (which also turns NaN into `0`), a rebase for lanes ≥ `2^31`, and an all-ones fix-up for overflow (or `vcvttps2udq` with a mask on AVX-512 hosts) — but never records `SAT`. -- **`VSCR[SAT]` sticky.** Cleared only by [`mtvscr`](mtvscr.md). +- **`VSCR[SAT]` sticky.** Cleared only by [`mtvscr`](../control/mtvscr.md). - **Rounding is truncate-toward-zero.** Always. - **`VSCR[NJ]` flushes denormal inputs to zero before scaling** (Xenon default). - **Big-endian word lanes.** Lane 0 is the most-significant word. @@ -130,7 +130,7 @@ int InstrEmit_vctuxs_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb, - [`vctsxs`](vctsxs.md) — same shape, signed destination. - [`vcfsx`](vcfsx.md), [`vcfux`](vcfux.md) — inverse direction. - [`vrfin`](vrfin.md), [`vrfip`](vrfip.md), [`vrfim`](vrfim.md), [`vrfiz`](vrfiz.md) — float-to-float rounding modes. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear `VSCR[SAT]`. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear `VSCR[SAT]`. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vmrghb.md b/tools/ppc-manual/vmx/vmrghb.md index 5831faad..33e19347 100644 --- a/tools/ppc-manual/vmx/vmrghb.md +++ b/tools/ppc-manual/vmx/vmrghb.md @@ -110,7 +110,7 @@ int InstrEmit_vmrghb(PPCHIRBuilder& f, const InstrData& i) { ## Special Cases & Edge Conditions - **Interleave the high (most-significant) eight bytes** of two vectors. After execution, `VD = {VA[0], VB[0], VA[1], VB[1], …, VA[7], VB[7]}`, i.e. the eight high-order bytes of `VA` are interleaved with the eight high-order bytes of `VB`. Because lane 0 is the most-significant byte (big-endian indexing), "high" means the byte that appears at the lowest address after `stvx`. -- **Pairs with [`vmrglb`](vmrglb.md).** Together they cover all 32 input bytes — `vmrghb` produces output of bytes 0..7 from each source, `vmrglb` of bytes 8..15. Two `vmrg*` instructions plus a [`stvx`](stvx.md) of each output produces the AoS-from-SoA transpose. +- **Pairs with [`vmrglb`](vmrglb.md).** Together they cover all 32 input bytes — `vmrghb` produces output of bytes 0..7 from each source, `vmrglb` of bytes 8..15. Two `vmrg*` instructions plus a [`stvx`](../memory/stvx.md) of each output produces the AoS-from-SoA transpose. - **Useful for unpacking 8-bit channels.** `vmrghb vRG, vR, vG` followed by `vmrghb vRGBA, vRG, vBA` interleaves four byte-streams into RGBA pixels. - **No `VSCR` interaction, no XER, no exceptions.** Pure permute. - **Aliasing legal.** `vmrghb v3, v3, v3` doubles each high byte of `v3`. diff --git a/tools/ppc-manual/vmx/vmrglh.md b/tools/ppc-manual/vmx/vmrglh.md index 9e492fa7..ed5ec79a 100644 --- a/tools/ppc-manual/vmx/vmrglh.md +++ b/tools/ppc-manual/vmx/vmrglh.md @@ -109,7 +109,7 @@ int InstrEmit_vmrglh(PPCHIRBuilder& f, const InstrData& i) { ## Special Cases & Edge Conditions - **Interleave the low (least-significant) four halves** of two vectors: `VD = {VA[4], VB[4], VA[5], VB[5], VA[6], VB[6], VA[7], VB[7]}`. -- **Pairs with [`vmrghh`](vmrghh.md)** to interleave the entire 8-half source range. The two instructions plus a [`stvx`](stvx.md) of each result produces an interleaved 16-half stream from two 8-half streams. +- **Pairs with [`vmrghh`](vmrghh.md)** to interleave the entire 8-half source range. The two instructions plus a [`stvx`](../memory/stvx.md) of each result produces an interleaved 16-half stream from two 8-half streams. - **Common usage.** Stereo Q15 audio interleave (low half of stream); paired with `vupklsh` for sign-extending unpack. - **No `VSCR` interaction, no XER, no exceptions.** Pure permute. - **Aliasing legal.** diff --git a/tools/ppc-manual/vmx/vmsumshs.md b/tools/ppc-manual/vmx/vmsumshs.md index f8730e2c..76916984 100644 --- a/tools/ppc-manual/vmx/vmsumshs.md +++ b/tools/ppc-manual/vmx/vmsumshs.md @@ -112,7 +112,7 @@ int InstrEmit_vmsumshs(PPCHIRBuilder& f, const InstrData& i) { ``` Two signed-half × signed-half products plus a signed-word accumulator, clamped to `int32`. - **Wide-then-clamp ordering.** The IBM specification accumulates the full sum and clamps only the *final* result to `int32`, which avoids spurious mid-sum saturation that would happen if the products were clamped individually. ⚠️ Canary does not implement `vmsumshs`: its emitter is `XEINSTRNOTIMPLEMENTED`, so translating one logs "Unimplemented instr" and, with the default `break_on_unimplemented_instructions`, breaks. -- **`VSCR[SAT]` is sticky-set** if any of the four lane sums saturates. Cleared only via [`mtvscr`](mtvscr.md). +- **`VSCR[SAT]` is sticky-set** if any of the four lane sums saturates. Cleared only via [`mtvscr`](../control/mtvscr.md). - **Big-endian half lanes.** Lane 0 is the most-significant half. - **No XER, no exceptions.** - **Aliasing legal.** @@ -125,7 +125,7 @@ int InstrEmit_vmsumshs(PPCHIRBuilder& f, const InstrData& i) { - [`vmsumuhs`](vmsumuhs.md) — unsigned half multiply-sum, saturating. - [`vmsummbm`](vmsummbm.md), [`vmsumubm`](vmsumubm.md) — multiply-sum at byte width. - [`vaddsws`](vaddsws.md) — saturating word add for further accumulation. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear `VSCR[SAT]`. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear `VSCR[SAT]`. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vmsumuhs.md b/tools/ppc-manual/vmx/vmsumuhs.md index 693ddc39..2ac97af5 100644 --- a/tools/ppc-manual/vmx/vmsumuhs.md +++ b/tools/ppc-manual/vmx/vmsumuhs.md @@ -125,7 +125,7 @@ int InstrEmit_vmsumuhs(PPCHIRBuilder& f, const InstrData& i) { - [`vmsumshs`](vmsumshs.md) — signed half multiply-sum, saturating. - [`vmsumubm`](vmsumubm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum at byte width. - [`vadduws`](vadduws.md) — unsigned saturating word add for further accumulation. -- [`mtvscr`](mtvscr.md) / [`mfvscr`](mfvscr.md) — read or clear `VSCR[SAT]`. +- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear `VSCR[SAT]`. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vnmsubfp.md b/tools/ppc-manual/vmx/vnmsubfp.md index 90e16782..7014721d 100644 --- a/tools/ppc-manual/vmx/vnmsubfp.md +++ b/tools/ppc-manual/vmx/vnmsubfp.md @@ -164,7 +164,7 @@ int InstrEmit_vnmsubfp128(PPCHIRBuilder& f, const InstrData& i) { - **No FPSCR effect.** Unlike scalar `fnmsub[s]`, `vnmsubfp` does not touch FPSCR. - **NaN propagation.** A NaN in any of `VA`, `VB`, or `VC` yields a NaN in the corresponding lane. Sign-of-NaN is unspecified; in Canary it is whatever the host multiply-subtract produced, with the sign flipped by `Neg`. - **Big-endian lane indexing.** Lane 0 is the MSB-most 4 bytes. -- **VMX128 sibling: [`vnmsubfp128`](vnmsubfp128.md).** Identical operation with access to `v0..v127`. +- **VMX128 sibling: `vnmsubfp128`.** Identical operation with access to `v0..v127`. - **No `Rc` bit** on this opcode; it never touches CR. ## Related Instructions diff --git a/tools/ppc-manual/vmx/vor.md b/tools/ppc-manual/vmx/vor.md index 0ddfeb03..e13ae0d7 100644 --- a/tools/ppc-manual/vmx/vor.md +++ b/tools/ppc-manual/vmx/vor.md @@ -175,7 +175,7 @@ int InstrEmit_vor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **`vor VD, VA, VA` is the idiomatic register move.** No dedicated "vmr" exists in base Altivec; compilers recognise the `vor v3, v4, v4` pattern as a move and schedule accordingly. - **Aliasing is legal.** `vor v3, v3, v4` merges the mask in `v4` into `v3`. - **No flags, no VSCR effect.** -- **VMX128 sibling [`vor128`](vor128.md).** Same operation, wider register file. +- **VMX128 sibling `vor128`.** Same operation, wider register file. - **Common pattern: ORing a compare mask with a data vector** to force specific lanes to all-ones without needing a select. ## Related Instructions diff --git a/tools/ppc-manual/vmx/vpkshss.md b/tools/ppc-manual/vmx/vpkshss.md index 36588a0a..c369a143 100644 --- a/tools/ppc-manual/vmx/vpkshss.md +++ b/tools/ppc-manual/vmx/vpkshss.md @@ -187,7 +187,7 @@ int InstrEmit_vpkshss_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Signed vs. unsigned output.** `vpkshss` has signed input and signed output. Compare with [`vpkshus`](vpkshus.md), which keeps signed input but clamps to `uint8` (`[0, 255]`). - **`VSCR[SAT]` is sticky.** Once set it remains set until an `mtvscr` clears it. Software that needs a per-block saturation signal must clear before the kernel and test after. - **No `Rc`, no XER / FPSCR.** -- **VMX128 sibling [`vpkshss128`](vpkshss128.md).** Same semantics, wider register file. +- **VMX128 sibling `vpkshss128`.** Same semantics, wider register file. ## Related Instructions diff --git a/tools/ppc-manual/vmx/vpkshus.md b/tools/ppc-manual/vmx/vpkshus.md index 50370dd7..3111aa26 100644 --- a/tools/ppc-manual/vmx/vpkshus.md +++ b/tools/ppc-manual/vmx/vpkshus.md @@ -186,7 +186,7 @@ int InstrEmit_vpkshus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Difference from [`vpkshss`](vpkshss.md).** Both take signed half-words; `shss` clamps to `int8`, `shus` clamps to `uint8`. Choose `shus` when the signed negative half is not physically meaningful (e.g. after subtracting a clamped-at-zero value). - **`VSCR[SAT]` is sticky.** - **No `Rc`, no XER / FPSCR.** -- **VMX128 sibling [`vpkshus128`](vpkshus128.md).** Same behaviour with wider register file. +- **VMX128 sibling `vpkshus128`.** Same behaviour with wider register file. ## Related Instructions @@ -194,7 +194,7 @@ int InstrEmit_vpkshus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - [`vpkuhus`](vpkuhus.md) — unsigned input → unsigned byte. - [`vpkuhum`](vpkuhum.md) — unsigned input, truncating (modulo) pack. - [`vpkswus`](vpkswus.md) — the word → half-word signed→unsigned analogue. -- [`vupkhub`](vupkhub.md)-family unpacks (if present) — the inverse. +- `vupkhub`-family unpacks (if present) — the inverse. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vpkswss.md b/tools/ppc-manual/vmx/vpkswss.md index 2ad2d0a2..e00fa8c1 100644 --- a/tools/ppc-manual/vmx/vpkswss.md +++ b/tools/ppc-manual/vmx/vpkswss.md @@ -187,7 +187,7 @@ int InstrEmit_vpkswss_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Signed vs. unsigned output.** `vpkswss` preserves sign; [`vpkswus`](vpkswus.md) clamps the same signed-word input to `uint16`. - **`VSCR[SAT]` is sticky.** - **No `Rc`, no XER / FPSCR.** -- **VMX128 sibling [`vpkswss128`](vpkswss128.md).** +- **VMX128 sibling `vpkswss128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vpkswus.md b/tools/ppc-manual/vmx/vpkswus.md index 51bdf87c..5fb64eff 100644 --- a/tools/ppc-manual/vmx/vpkswus.md +++ b/tools/ppc-manual/vmx/vpkswus.md @@ -186,7 +186,7 @@ int InstrEmit_vpkswus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Choose over [`vpkswss`](vpkswss.md)** when negative results shouldn't survive — e.g. clamped colour or intensity values that happen to have arrived in `int32` form. - **`VSCR[SAT]` is sticky.** - **No `Rc`, no XER / FPSCR.** -- **VMX128 sibling [`vpkswus128`](vpkswus128.md).** +- **VMX128 sibling `vpkswus128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vpkuhum.md b/tools/ppc-manual/vmx/vpkuhum.md index 9a7b112e..94d2738f 100644 --- a/tools/ppc-manual/vmx/vpkuhum.md +++ b/tools/ppc-manual/vmx/vpkuhum.md @@ -180,14 +180,14 @@ int InstrEmit_vpkuhum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Lane-count doubling.** 16 half-word lanes → 16 byte lanes, `VA`'s 8 half-words into `VD.b[0..7]` and `VB`'s 8 into `VD.b[8..15]`. - **Cheap "low-byte extract" primitive.** Often used to repack per-channel results after a half-word arithmetic step. Contrast with shifting + masking. - **No `Rc`, no XER.** -- **VMX128 sibling [`vpkuhum128`](vpkuhum128.md).** +- **VMX128 sibling `vpkuhum128`.** ## Related Instructions - [`vpkuhus`](vpkuhus.md) — the saturating sibling. - [`vpkuwum`](vpkuwum.md) — word → half-word modulo pack. - [`vpkshss`](vpkshss.md), [`vpkshus`](vpkshus.md) — signed half-word packs. -- [`vupkhub`](vupkhub.md) / [`vupklub`](vupklub.md) (if present) — zero-extending byte → half-word unpacks that reverse this op. +- `vupkhub` / `vupklub` (if present) — zero-extending byte → half-word unpacks that reverse this op. - [`vperm`](vperm.md) — general-purpose alternative when the packing pattern is irregular. ## IBM Reference diff --git a/tools/ppc-manual/vmx/vpkuhus.md b/tools/ppc-manual/vmx/vpkuhus.md index 86f7a4bd..ba2c90fa 100644 --- a/tools/ppc-manual/vmx/vpkuhus.md +++ b/tools/ppc-manual/vmx/vpkuhus.md @@ -186,7 +186,7 @@ int InstrEmit_vpkuhus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Pair with [`vpkuhum`](vpkuhum.md)** when saturation is not desired (truncate the low byte instead). - **`VSCR[SAT]` is sticky.** - **No `Rc`, no XER.** -- **VMX128 sibling [`vpkuhus128`](vpkuhus128.md).** +- **VMX128 sibling `vpkuhus128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vpkuwum.md b/tools/ppc-manual/vmx/vpkuwum.md index 24963f17..6fb18ea1 100644 --- a/tools/ppc-manual/vmx/vpkuwum.md +++ b/tools/ppc-manual/vmx/vpkuwum.md @@ -180,7 +180,7 @@ int InstrEmit_vpkuwum_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **`VSCR[SAT]` never touched** (modulo variant). Use [`vpkuwus`](vpkuwus.md) for saturation. - **Cheap low-half extract.** Typical after a 32-bit lane accumulator is "narrowed" back down to 16-bit for storage. - **No `Rc`, no XER.** -- **VMX128 sibling [`vpkuwum128`](vpkuwum128.md).** +- **VMX128 sibling `vpkuwum128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vpkuwus.md b/tools/ppc-manual/vmx/vpkuwus.md index c126b3be..eef48a13 100644 --- a/tools/ppc-manual/vmx/vpkuwus.md +++ b/tools/ppc-manual/vmx/vpkuwus.md @@ -186,7 +186,7 @@ int InstrEmit_vpkuwus_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, - **Pair with [`vpkuwum`](vpkuwum.md)** when a modulo wrap is required. - **`VSCR[SAT]` is sticky.** - **No `Rc`, no XER.** -- **VMX128 sibling [`vpkuwus128`](vpkuwus128.md).** +- **VMX128 sibling `vpkuwus128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrefp.md b/tools/ppc-manual/vmx/vrefp.md index 53786b45..f076b1fd 100644 --- a/tools/ppc-manual/vmx/vrefp.md +++ b/tools/ppc-manual/vmx/vrefp.md @@ -161,7 +161,7 @@ int InstrEmit_vrefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **IEEE-754 binary32 lanes; `VSCR[NJ]` honoured** (denormals flush to zero when `NJ = 1`). - **No VSCR[SAT] update, no FPSCR update, no exception.** Division by zero yields ±∞; division of zero yields ±∞ too (same sign convention). - **Big-endian lane indexing.** -- **VMX128 sibling [`vrefp128`](vrefp128.md).** +- **VMX128 sibling `vrefp128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrfim.md b/tools/ppc-manual/vmx/vrfim.md index f9241d39..64dcd8a4 100644 --- a/tools/ppc-manual/vmx/vrfim.md +++ b/tools/ppc-manual/vmx/vrfim.md @@ -162,7 +162,7 @@ int InstrEmit_vrfim_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **NaN propagation.** NaN input → NaN output. `±∞` → `±∞`. - **No VSCR[SAT], no FPSCR update.** No "inexact" trap flag; this is the VMX rounding variant that deliberately ignores FPSCR's rounding mode. - **Big-endian lane indexing.** -- **VMX128 sibling [`vrfim128`](vrfim128.md).** +- **VMX128 sibling `vrfim128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrfin.md b/tools/ppc-manual/vmx/vrfin.md index d2abe035..184e142c 100644 --- a/tools/ppc-manual/vmx/vrfin.md +++ b/tools/ppc-manual/vmx/vrfin.md @@ -162,7 +162,7 @@ int InstrEmit_vrfin_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **NaN and ±∞** pass through unchanged. - **No VSCR[SAT], no FPSCR update.** - **Big-endian lane indexing.** -- **VMX128 sibling [`vrfin128`](vrfin128.md).** +- **VMX128 sibling `vrfin128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrfip.md b/tools/ppc-manual/vmx/vrfip.md index 218a9092..8b6a55a2 100644 --- a/tools/ppc-manual/vmx/vrfip.md +++ b/tools/ppc-manual/vmx/vrfip.md @@ -162,7 +162,7 @@ int InstrEmit_vrfip_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **NaN and ±∞** pass through. - **No VSCR[SAT], no FPSCR update.** - **Big-endian lane indexing.** -- **VMX128 sibling [`vrfip128`](vrfip128.md).** +- **VMX128 sibling `vrfip128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrfiz.md b/tools/ppc-manual/vmx/vrfiz.md index 345d09b1..08a7737f 100644 --- a/tools/ppc-manual/vmx/vrfiz.md +++ b/tools/ppc-manual/vmx/vrfiz.md @@ -162,7 +162,7 @@ int InstrEmit_vrfiz_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **NaN and ±∞** pass through. - **No VSCR[SAT], no FPSCR update.** `vrfiz` is the VMX analogue of C's `truncf`. - **Big-endian lane indexing.** -- **VMX128 sibling [`vrfiz128`](vrfiz128.md).** +- **VMX128 sibling `vrfiz128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrlw.md b/tools/ppc-manual/vmx/vrlw.md index 13d6b7d7..a7a7a976 100644 --- a/tools/ppc-manual/vmx/vrlw.md +++ b/tools/ppc-manual/vmx/vrlw.md @@ -166,7 +166,7 @@ int InstrEmit_vrlw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **Big-endian word lanes.** Lane 0 is the most significant 4 bytes. - **No overflow, no saturation.** - **No `Rc`, no XER, no VSCR effect.** -- **VMX128 sibling [`vrlw128`](vrlw128.md)** — same op with the wider register file. +- **VMX128 sibling `vrlw128`** — same op with the wider register file. - **Building block for [`vrlimi128`](../vmx128/vrlimi128.md).** VMX128 fuses a rotate with an immediate-masked insert for cheaper bitfield shuffles; `vrlw` is the plain variant that the XDK uses for scalar-style 32-bit rotates. ## Related Instructions diff --git a/tools/ppc-manual/vmx/vrsqrtefp.md b/tools/ppc-manual/vmx/vrsqrtefp.md index e977f1b3..d4aab6c4 100644 --- a/tools/ppc-manual/vmx/vrsqrtefp.md +++ b/tools/ppc-manual/vmx/vrsqrtefp.md @@ -168,7 +168,7 @@ int InstrEmit_vrsqrtefp_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **IEEE-754 binary32; `VSCR[NJ]` honoured.** - **No VSCR[SAT], no FPSCR update, no exception.** - **Big-endian lane indexing.** -- **VMX128 sibling [`vrsqrtefp128`](vrsqrtefp128.md).** +- **VMX128 sibling `vrsqrtefp128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vsldoi.md b/tools/ppc-manual/vmx/vsldoi.md index 3ef75a7a..d01cba58 100644 --- a/tools/ppc-manual/vmx/vsldoi.md +++ b/tools/ppc-manual/vmx/vsldoi.md @@ -183,7 +183,7 @@ int InstrEmit_vsldoi128(PPCHIRBuilder& f, const InstrData& i) { - **Unaligned-load idiom.** `vsldoi` is the static-offset counterpart to the dynamic `lvsl` + `vperm` pattern. When the misalignment is known, emit `vsldoi vD, vAL, vAH, SHB` after two aligned `lvx` loads. - **Big-endian byte indexing.** Lane 0 is the MSB. - **No flags, no VSCR.** -- **VMX128 sibling [`vsldoi128`](vsldoi128.md)** with the wider register file; same 4-bit `SHB` immediate. +- **VMX128 sibling `vsldoi128`** with the wider register file; same 4-bit `SHB` immediate. ## Related Instructions diff --git a/tools/ppc-manual/vmx/vslo.md b/tools/ppc-manual/vmx/vslo.md index f70cc977..b2f301c1 100644 --- a/tools/ppc-manual/vmx/vslo.md +++ b/tools/ppc-manual/vmx/vslo.md @@ -176,7 +176,7 @@ int InstrEmit_vslo_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **Pair with [`vsl`](vsl.md) for full bit-level shifts.** `vslo` contributes the byte-granular part; `vsl` contributes the 0..7 residual bits. - **Big-endian.** "Left" = toward MSB = toward `VD.b[0]`. - **No flags, no VSCR.** -- **VMX128 sibling [`vslo128`](vslo128.md).** +- **VMX128 sibling `vslo128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vslw.md b/tools/ppc-manual/vmx/vslw.md index 8b400ea8..bdc5a895 100644 --- a/tools/ppc-manual/vmx/vslw.md +++ b/tools/ppc-manual/vmx/vslw.md @@ -170,7 +170,7 @@ int InstrEmit_vslw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **Zero-fill right.** Arithmetic right shift is [`vsraw`](vsraw.md). - **Big-endian word indexing.** - **No flags, no VSCR.** -- **VMX128 sibling [`vslw128`](vslw128.md).** +- **VMX128 sibling `vslw128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vspltisw.md b/tools/ppc-manual/vmx/vspltisw.md index d01b0148..1f479e18 100644 --- a/tools/ppc-manual/vmx/vspltisw.md +++ b/tools/ppc-manual/vmx/vspltisw.md @@ -176,7 +176,7 @@ int InstrEmit_vspltisw_(PPCHIRBuilder& f, uint32_t vd, uint32_t uimm) { - **Constant-generation primitive.** `vspltisw vD, 0` zeroes every lane; `vspltisw vD, -1` generates `{0xFFFFFFFF, …}` (the all-ones vector); `vspltisw vD, 1` is `{1, 1, 1, 1}` — useful for "lane index = 0, 1, 2, 3" constructions via an `lvewx`-style preload followed by this. - **No source register.** - **No flags, no VSCR.** -- **VMX128 sibling [`vspltisw128`](vspltisw128.md).** +- **VMX128 sibling `vspltisw128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vspltw.md b/tools/ppc-manual/vmx/vspltw.md index 2e9323f0..54d7846d 100644 --- a/tools/ppc-manual/vmx/vspltw.md +++ b/tools/ppc-manual/vmx/vspltw.md @@ -165,7 +165,7 @@ int InstrEmit_vspltw_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb, - **Big-endian index.** `UIMM = 0` → `VB.w[0]` (most significant word). - **Typical use: broadcast a float or a 32-bit constant** (e.g. splatting a scalar result before feeding it to a per-lane multiply). - **No flags, no VSCR.** -- **VMX128 sibling [`vspltw128`](vspltw128.md).** +- **VMX128 sibling `vspltw128`.** - **Compares with [`vpermwi128`](../vmx128/vpermwi128.md):** `vpermwi128` generalises word splat to any 4-of-4 permutation using an 8-bit immediate (2 bits per output word). ## Related Instructions diff --git a/tools/ppc-manual/vmx/vsraw.md b/tools/ppc-manual/vmx/vsraw.md index a047e6c0..00b2c39f 100644 --- a/tools/ppc-manual/vmx/vsraw.md +++ b/tools/ppc-manual/vmx/vsraw.md @@ -166,7 +166,7 @@ int InstrEmit_vsraw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **Sign extension** — distinct from [`vsrw`](vsrw.md) (zero-fill). - **Big-endian word lanes.** - **No flags, no VSCR.** -- **VMX128 sibling [`vsraw128`](vsraw128.md).** +- **VMX128 sibling `vsraw128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vsro.md b/tools/ppc-manual/vmx/vsro.md index 0d3b5eb3..687449c2 100644 --- a/tools/ppc-manual/vmx/vsro.md +++ b/tools/ppc-manual/vmx/vsro.md @@ -176,7 +176,7 @@ int InstrEmit_vsro_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **Pair with [`vsr`](vsr.md) for full bit-level shifts.** `vsro` handles bytes; `vsr` handles the 0..7 residual. - **Big-endian.** "Right" = toward LSB end (`VD.b[15]`). - **No flags, no VSCR.** -- **VMX128 sibling [`vsro128`](vsro128.md).** +- **VMX128 sibling `vsro128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vsrw.md b/tools/ppc-manual/vmx/vsrw.md index 45c2438f..479546ba 100644 --- a/tools/ppc-manual/vmx/vsrw.md +++ b/tools/ppc-manual/vmx/vsrw.md @@ -166,7 +166,7 @@ int InstrEmit_vsrw_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **Zero-fill.** Use [`vsraw`](vsraw.md) for sign-preserving right shift. - **Big-endian word lanes.** - **No flags, no VSCR.** -- **VMX128 sibling [`vsrw128`](vsrw128.md).** +- **VMX128 sibling `vsrw128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vsubcuw.md b/tools/ppc-manual/vmx/vsubcuw.md index 22f5d2c0..0a32d6d9 100644 --- a/tools/ppc-manual/vmx/vsubcuw.md +++ b/tools/ppc-manual/vmx/vsubcuw.md @@ -107,7 +107,7 @@ int InstrEmit_vsubcuw(PPCHIRBuilder& f, const InstrData& i) { ## Special Cases & Edge Conditions - **"Borrow out" producer for unsigned word subtract.** Each of the 4 lanes produces `1` if `VA.w[i] >= VB.w[i]` (no borrow) and `0` otherwise. This is an **inverted** borrow — conventional borrow would be `1` on underflow, but Altivec's `vsubcuw` returns the opposite to match the `XER[CA]` convention used by scalar `subfc` / `subfe`. -- **Complements [`vadduwm`](vadduwm.md) / [`vaddcuw`](vaddcuw.md)** for 256-bit (or wider) multi-precision arithmetic. After the lane subtract, chain the 4-bit borrow vector into the next word via [`vsubeuwm`](vsubeuwm.md)-style helpers (or manual software glue, since Altivec has no direct `sube`). +- **Complements [`vadduwm`](vadduwm.md) / [`vaddcuw`](vaddcuw.md)** for 256-bit (or wider) multi-precision arithmetic. After the lane subtract, chain the 4-bit borrow vector into the next word via `vsubeuwm`-style helpers (or manual software glue, since Altivec has no direct `sube`). - **No saturation, no flags, no VSCR effect.** Despite being in the "carry" family, `vsubcuw` doesn't touch `VSCR[SAT]`. - **Big-endian word lanes.** - **No VMX128 sibling.** diff --git a/tools/ppc-manual/vmx/vsubfp.md b/tools/ppc-manual/vmx/vsubfp.md index 3bd376e9..6d7d75b0 100644 --- a/tools/ppc-manual/vmx/vsubfp.md +++ b/tools/ppc-manual/vmx/vsubfp.md @@ -163,7 +163,7 @@ int InstrEmit_vsubfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **`±∞ − ±∞` → NaN.** No exception, no VSCR[SAT] set. - **No FPSCR update.** VMX float ops are independent of the scalar FPU's status register. - **Big-endian lane indexing.** -- **VMX128 sibling [`vsubfp128`](vsubfp128.md).** +- **VMX128 sibling `vsubfp128`.** - **Aliasing legal.** `vsubfp v3, v3, v4` is fine. ## Related Instructions diff --git a/tools/ppc-manual/vmx/vupkhsb.md b/tools/ppc-manual/vmx/vupkhsb.md index 7c96edac..e7c7cb90 100644 --- a/tools/ppc-manual/vmx/vupkhsb.md +++ b/tools/ppc-manual/vmx/vupkhsb.md @@ -164,7 +164,7 @@ int InstrEmit_vupkhsb128(PPCHIRBuilder& f, const InstrData& i) { - **Inverse of the high half of [`vpkshss`](vpkshss.md) / [`vpkshus`](vpkshus.md)** (within the `int8` range — larger `int16`s cannot survive a round-trip through a saturating pack). - **Big-endian lane ordering** — `VB.b[0]` becomes `VD.h[0]`. - **No saturation, no flags, no VSCR effect.** -- **VMX128 sibling [`vupkhsb128`](vupkhsb128.md).** +- **VMX128 sibling `vupkhsb128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vupkhsh.md b/tools/ppc-manual/vmx/vupkhsh.md index 4a9b2976..db0e41bd 100644 --- a/tools/ppc-manual/vmx/vupkhsh.md +++ b/tools/ppc-manual/vmx/vupkhsh.md @@ -115,7 +115,7 @@ int InstrEmit_vupkhsh_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **Inverse of the high half of [`vpkswss`](vpkswss.md)** (within the `int16` range). - **Big-endian lane ordering.** - **No saturation, no flags, no VSCR effect.** -- **VMX128 sibling [`vupkhsh128`](vupkhsh128.md).** +- **VMX128 sibling `vupkhsh128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vupklsb.md b/tools/ppc-manual/vmx/vupklsb.md index af800e76..7b63dd25 100644 --- a/tools/ppc-manual/vmx/vupklsb.md +++ b/tools/ppc-manual/vmx/vupklsb.md @@ -164,7 +164,7 @@ int InstrEmit_vupklsb128(PPCHIRBuilder& f, const InstrData& i) { - **Inverse of the low half of [`vpkshss`](vpkshss.md) / [`vpkshus`](vpkshus.md)** (within the `int8` range). - **Big-endian lane ordering.** - **No saturation, no flags, no VSCR effect.** -- **VMX128 sibling [`vupklsb128`](vupklsb128.md).** +- **VMX128 sibling `vupklsb128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vupklsh.md b/tools/ppc-manual/vmx/vupklsh.md index ce719fbe..c0ba465d 100644 --- a/tools/ppc-manual/vmx/vupklsh.md +++ b/tools/ppc-manual/vmx/vupklsh.md @@ -115,7 +115,7 @@ int InstrEmit_vupklsh_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb) { - **Inverse of the low half of [`vpkswss`](vpkswss.md)** (within the `int16` range). - **Big-endian lane ordering.** - **No saturation, no flags, no VSCR effect.** -- **VMX128 sibling [`vupklsh128`](vupklsh128.md).** +- **VMX128 sibling `vupklsh128`.** ## Related Instructions diff --git a/tools/ppc-manual/vmx/vxor.md b/tools/ppc-manual/vmx/vxor.md index 7df3a786..acfc1d7f 100644 --- a/tools/ppc-manual/vmx/vxor.md +++ b/tools/ppc-manual/vmx/vxor.md @@ -177,7 +177,7 @@ int InstrEmit_vxor_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { - **`vxor VD, VD, VD` is the canonical "vector zero" idiom.** Every Xenon compiler uses this to materialise the all-zero vector; Canary special-cases it at translate time — when `VA == VB` it stores a zero vector without reading the register. - **Aliasing legal.** `vxor v3, v3, v4` toggles bits from `v4` into `v3`. - **No flags, no VSCR.** -- **VMX128 sibling [`vxor128`](vxor128.md).** Identical semantics; wider register file. +- **VMX128 sibling `vxor128`.** Identical semantics; wider register file. - **Compare-then-XOR** is the cheapest "mask flip" when `vnor` is not wanted (e.g. to toggle only certain bits, not every bit). ## Related Instructions