# `stfd` — Store Floating-Point Double > **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xd8000000` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `stfd` | `stfd` | — | Store Floating-Point Double | | `stfdu` | `stfdu` | — | Store Floating-Point Double with Update | | `stfdux` | `stfdux` | — | Store Floating-Point Double with Update Indexed | | `stfdx` | `stfdx` | — | Store Floating-Point Double Indexed | ## Syntax ```asm stfd [FS], [d]([RA0]) stfdu [FS], [d]([RA]) stfdux [FS], [RA], [RB] stfdx [FS], [RA0], [RB] ``` ## Encoding ### `stfd` — form `D` - **Opcode word:** `0xd8000000` - **Primary opcode (bits 0–5):** `54` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `stfdu` — form `D` - **Opcode word:** `0xdc000000` - **Primary opcode (bits 0–5):** `55` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `stfdux` — form `X` - **Opcode word:** `0x7c0005ee` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `759` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ### `stfdx` — form `X` - **Opcode word:** `0x7c0005ae` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `727` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ## Operands | Field | Role | Description | | --- | --- | --- | | `FS` | stfd: read; stfdu: read; stfdux: read; stfdx: read | Source floating-point register. | | `RA0` | stfd: read; stfdx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. | | `d` | stfd: read; stfdu: read | 16-bit signed displacement (`d`) added to the base address register. | | `RA` | stfdu: read; stfdu: write; stfdux: read; stfdux: write | Source GPR (`r0`–`r31`). | | `RB` | stfdux: read; stfdx: read | Source GPR. | ## Register Effects ### `stfd` - **Reads (always):** `FS`, `RA0`, `d` - **Reads (conditional):** _none_ - **Writes (always):** _none_ - **Writes (conditional):** _none_ ### `stfdu` - **Reads (always):** `FS`, `RA`, `d` - **Reads (conditional):** _none_ - **Writes (always):** `RA` - **Writes (conditional):** _none_ ### `stfdux` - **Reads (always):** `FS`, `RA`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `RA` - **Writes (conditional):** _none_ ### `stfdx` - **Reads (always):** `FS`, `RA0`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** _none_ - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` EA <- (RA|0) + EXTS(d) MEM(EA, 8) <- (FRS) ``` ## C Translation Example ```c /* No hand-written C yet. Translate the Canary emitter snapshot */ /* under Implementation References; its HIR maps directly: */ /* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */ /* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */ /* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */ /* wrap them in f.ByteSwap for the big-endian guest value */ /* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */ /* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */ /* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`stfd`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfd"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1014`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1014) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:237`](../../../crates/sylpheed-ppc/src/opcode.rs#L237) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:492`](../../../crates/sylpheed-ppc/src/decoder.rs#L492)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfd(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + EXTS(D) // MEM(EA, 8) <- (FRS) Value* ea = CalculateEA_0_i(f, i.D.RA, XEEXTS16(i.D.DS)); f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.D.RT), INT64_TYPE))); return 0; } ```
**`stfdu`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfdu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1026`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1026) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:238`](../../../crates/sylpheed-ppc/src/opcode.rs#L238) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:493`](../../../crates/sylpheed-ppc/src/decoder.rs#L493)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfdu(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + EXTS(D) // MEM(EA, 8) <- (FRS) // RA <- EA Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS)); f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.D.RT), INT64_TYPE))); StoreEA(f, i.D.RA, ea); return 0; } ```
**`stfdux`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfdux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1036`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1036) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:239`](../../../crates/sylpheed-ppc/src/opcode.rs#L239) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:952`](../../../crates/sylpheed-ppc/src/decoder.rs#L952)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfdux(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + (RB) // MEM(EA, 8) <- (FRS) // RA <- EA Value* ea = CalculateEA(f, i.X.RA, i.X.RB); f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.X.RT), INT64_TYPE))); StoreEA(f, i.X.RA, ea); return 0; } ```
**`stfdx`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfdx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1046`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1046) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:240`](../../../crates/sylpheed-ppc/src/opcode.rs#L240) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:951`](../../../crates/sylpheed-ppc/src/decoder.rs#L951)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfdx(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + (RB) // MEM(EA, 8) <- (FRS) Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); f.Store(ea, f.ByteSwap(f.Cast(f.LoadFPR(i.X.RT), INT64_TYPE))); return 0; } ```
## Special Cases & Edge Conditions - **Bit-exact double store.** Writes the 64-bit IEEE binary64 contents of `FRS` directly to memory; no rounding, no format conversion. Canary reinterprets the FPR as a 64-bit integer (`Cast`) and stores it byte-swapped, which preserves the exact bit pattern (including signalling NaNs). - **No FPSCR side effects.** Like [`lfd`](lfd.md), `stfd` cannot raise IEEE exceptions: there is no rounding step. Contrast [`stfs`](stfs.md), where double→single rounding **can** raise inexact / overflow / underflow. - **`RA0` (non-update forms).** `RA = 0` in `stfd` and `stfdx` selects literal zero. Update forms `stfdu` / `stfdux` invoke `RA = 0` as an invalid form. - **Update-form post-write.** `stfdu` / `stfdux` write the computed `EA` back to `RA` after the store. No `FRS` / `RA` collision possible — `RS` is an FPR, `RA` is a GPR. - **Big-endian write.** Byte at `EA` is the FPR's most-significant byte (sign + part of exponent), byte at `EA+7` is the least-significant mantissa byte. Canary byte-swaps before the host store. - **Alignment.** Xenon tolerates unaligned 8-byte FP stores. PowerISA permits implementations to raise alignment exceptions on cache-inhibited storage. - **MSR[FP] required.** Disabled FP unit raises Floating-Point Unavailable. ## Related Instructions - [`lfd`](lfd.md), [`lfdu`](lfd.md), [`lfdx`](lfd.md), [`lfdux`](lfd.md) — corresponding loads. - [`stfs`](stfs.md) — single-precision store with format conversion (can raise FPSCR). - [`stfiwx`](stfiwx.md) — store low 32 bits of FPR as integer word. - [`std`](std.md) — integer doubleword store (same width, GPR source). ## IBM Reference - [AIX 7.3 — `stfd` (Store Floating-Point Double)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfd-store-floating-point-double-instruction) - [AIX 7.3 — `stfdu` / `stfdx` / `stfdux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfdu-store-floating-point-double-update-instruction)