# `stfs` — Store Floating-Point Single > **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xd0000000` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `stfs` | `stfs` | — | Store Floating-Point Single | | `stfsu` | `stfsu` | — | Store Floating-Point Single with Update | | `stfsux` | `stfsux` | — | Store Floating-Point Single with Update Indexed | | `stfsx` | `stfsx` | — | Store Floating-Point Single Indexed | ## Syntax ```asm stfs [FS], [d]([RA0]) stfsu [FS], [d]([RA]) stfsux [FS], [RA], [RB] stfsx [FS], [RA], [RB] ``` ## Encoding ### `stfs` — form `D` - **Opcode word:** `0xd0000000` - **Primary opcode (bits 0–5):** `52` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `stfsu` — form `D` - **Opcode word:** `0xd4000000` - **Primary opcode (bits 0–5):** `53` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `stfsux` — form `X` - **Opcode word:** `0x7c00056e` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `695` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ### `stfsx` — form `X` - **Opcode word:** `0x7c00052e` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `663` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ## Operands | Field | Role | Description | | --- | --- | --- | | `FS` | stfs: read; stfsu: read; stfsux: read; stfsx: read | Source floating-point register. | | `RA0` | stfs: read; stfsx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. | | `d` | stfs: read; stfsu: read | 16-bit signed displacement (`d`) added to the base address register. | | `RA` | stfsu: read; stfsu: write; stfsux: read; stfsux: write | Source GPR (`r0`–`r31`). | | `RB` | stfsux: read; stfsx: read | Source GPR. | ## Register Effects ### `stfs` - **Reads (always):** `FS`, `RA0`, `d` - **Reads (conditional):** _none_ - **Writes (always):** _none_ - **Writes (conditional):** _none_ ### `stfsu` - **Reads (always):** `FS`, `RA`, `d` - **Reads (conditional):** _none_ - **Writes (always):** `RA` - **Writes (conditional):** _none_ ### `stfsux` - **Reads (always):** `FS`, `RA`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `RA` - **Writes (conditional):** _none_ ### `stfsx` - **Reads (always):** `FS`, `RA0`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** _none_ - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` EA <- (RA|0) + EXTS(d) MEM(EA, 4) <- SingleFromDouble(FRS) ``` ## C Translation Example ```c /* No hand-written C yet. Translate the Canary emitter snapshot */ /* under Implementation References; its HIR maps directly: */ /* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */ /* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */ /* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */ /* wrap them in f.ByteSwap for the big-endian guest value */ /* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */ /* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */ /* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`stfs`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfs"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1071`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1071) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:242`](../../../crates/sylpheed-ppc/src/opcode.rs#L242) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:490`](../../../crates/sylpheed-ppc/src/decoder.rs#L490)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfs(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + EXTS(D) // MEM(EA, 4) <- SINGLE(FRS) Value* ea = CalculateEA_0_i(f, i.D.RA, XEEXTS16(i.D.DS)); f.Store(ea, f.ByteSwap(f.Cast(f.Convert(f.LoadFPR(i.D.RT), FLOAT32_TYPE), INT32_TYPE))); return 0; } ```
**`stfsu`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfsu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1084`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1084) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:243`](../../../crates/sylpheed-ppc/src/opcode.rs#L243) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:491`](../../../crates/sylpheed-ppc/src/decoder.rs#L491)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfsu(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + EXTS(D) // MEM(EA, 4) <- SINGLE(FRS) // RA <- EA Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS)); f.Store(ea, f.ByteSwap(f.Cast(f.Convert(f.LoadFPR(i.D.RT), FLOAT32_TYPE), INT32_TYPE))); StoreEA(f, i.D.RA, ea); return 0; } ```
**`stfsux`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfsux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1095`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1095) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:244`](../../../crates/sylpheed-ppc/src/opcode.rs#L244) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:949`](../../../crates/sylpheed-ppc/src/decoder.rs#L949)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfsux(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + (RB) // MEM(EA, 4) <- SINGLE(FRS) // RA <- EA Value* ea = CalculateEA(f, i.X.RA, i.X.RB); f.Store(ea, f.ByteSwap(f.Cast(f.Convert(f.LoadFPR(i.X.RT), FLOAT32_TYPE), INT32_TYPE))); StoreEA(f, i.X.RA, ea); return 0; } ```
**`stfsx`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stfsx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1106`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1106) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:245`](../../../crates/sylpheed-ppc/src/opcode.rs#L245) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:947`](../../../crates/sylpheed-ppc/src/decoder.rs#L947)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_stfsx(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + (RB) // MEM(EA, 4) <- SINGLE(FRS) Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); f.Store(ea, f.ByteSwap(f.Cast(f.Convert(f.LoadFPR(i.X.RT), FLOAT32_TYPE), INT32_TYPE))); return 0; } ```
## Special Cases & Edge Conditions - **Double → single is a bit-level conversion, not a rounding.** `FRS` always holds an IEEE binary64; `stfs` does not round it under `FPSCR[RN]`. In the single-precision range it keeps `FRS[0:1]` and `FRS[5:34]` and drops the low significand bits; tiny values are denormalised by shifting — the store conversion of the PowerPC Programming Environments Manual, which Dolphin's `ConvertToSingle` implements. Canary instead converts with `vcvtsd2ss`, which rounds under the host rounding mode. The two agree whenever `FRS` already holds a single-precision value, the normal case after single-precision arithmetic. - **FPSCR side effects.** None. Like [`lfs`](lfs.md) / [`lfd`](lfd.md) / [`stfd`](stfd.md), `stfs` does not affect the FPSCR (AIX assembler reference). Canary sets no FPSCR bits here either. - **Out-of-range doubles.** Values larger than binary32's max (~3.4e38) round to ±∞; values smaller than min normal flush to ±0 or denormal per `FPSCR[NI]`. NaNs are quieted (the signalling bit drops). - **`RA0` (non-update forms).** `RA = 0` in `stfs` and `stfsx` selects literal zero. Update forms `stfsu` / `stfsux` invoke `RA = 0` as an invalid form. - **Update-form post-write.** `stfsu` / `stfsux` write `EA` back to `RA` after the store. - **Big-endian write.** 4 bytes most-significant-byte first. - **Alignment.** Xenon tolerates unaligned 4-byte FP stores; cache-inhibited storage may raise alignment exceptions on real hardware. - **MSR[FP] required.** Disabled FP unit raises Floating-Point Unavailable. ## Related Instructions - [`lfs`](lfs.md), [`lfsu`](lfs.md), [`lfsx`](lfs.md), [`lfsux`](lfs.md) — corresponding loads (single→double widening, can't raise exceptions). - [`stfd`](stfd.md) — double-precision store (no rounding, no FPSCR effects). - [`stfiwx`](stfiwx.md) — store-FP-as-integer-word. - [`stw`](stw.md) — integer word store (same width, GPR source). ## IBM Reference - [AIX 7.3 — `stfs` (Store Floating-Point Single)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfs-store-floating-point-single-instruction) - [AIX 7.3 — `stfsu` / `stfsx` / `stfsux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stfsu-store-floating-point-single-update-instruction)