# `stvebx` — Store Vector Element Byte Indexed

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00010e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stvebx` | `stvebx` | — | Store Vector Element Byte Indexed |

## Syntax

```asm
stvebx [VS], [RA0], [RB]
```

## Encoding

### `stvebx` — form `X`

- **Opcode word:** `0x7c00010e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `135`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VS` | stvebx: read | Source vector register (alias for VD on stores). |
| `RA0` | stvebx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stvebx: read | Source GPR. |

## Register Effects

### `stvebx`

- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`stvebx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvebx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:152`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L152)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:257`](../../../crates/sylpheed-ppc/src/opcode.rs#L257)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:893`](../../../crates/sylpheed-ppc/src/decoder.rs#L893)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_stvebx(PPCHIRBuilder& f, const InstrData& i) {
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  Value* el = f.And(f.Truncate(ea, INT8_TYPE), f.LoadConstantUint8(0xF));
  Value* v = f.Extract(f.LoadVR(i.X.RT), el, INT8_TYPE);
  f.Store(ea, v);
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Single-byte element store.** Architecturally `stvebx` writes exactly **one** byte from lane `EA mod 16` of `VS` to address `EA`. Other lanes are unaffected, and other memory bytes are unaffected.
- **Single-byte write in Canary.** Canary stores just the one element: the byte `VS.b[EA & 0xF]` at `EA`, leaving the rest of the line alone — the architectural granularity.
- **`RA0` semantics.** `RA = 0` selects literal zero.
- **No update form, no VMX128 sibling.** No `stvebux`; no `stvebx128` — single-byte stores were kept Altivec-only in the Xbox 360 extension.
- **Big-endian within the line.** Lane 0 of `VS` corresponds to the byte at the aligned base address.
- **Common idiom.** Pair with `vsplt*` to broadcast a value, then `stvebx` to write one byte. Less efficient than `stb` from a GPR; rare in compiled code.
- **Hardware fault model.** A protected or unmapped page raises a DSI exception just as for any store.

## Related Instructions

- [`stvehx`](stvehx.md), [`stvewx`](stvewx.md) — single half / single word element stores.
- [`stvx`](stvx.md), [`stvxl`](stvxl.md) — full 16-byte aligned vector stores.
- [`stvlx`](stvlx.md), [`stvrx`](stvrx.md) — store-left / store-right unaligned vector ops.
- [`lvebx`](lvebx.md) — symmetric single-byte load.

## IBM Reference

- [AIX 7.3 — `stvebx` (Store Vector Element Byte Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stvebx-store-vector-element-byte-indexed-instruction)
- `PowerISA v2.07B Book I` "Vector Facility" § "Vector Load and Store" for canonical per-byte semantics.