# `mtfsb0x` — Move to FPSCR Bit 0

> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0xfc00008c`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `mtfsb0` | `mtfsb0x` | — | Move to FPSCR Bit 0 |
| `mtfsb0.` | `mtfsb0x` | Rc=1 | Move to FPSCR Bit 0 |

## Syntax

```asm
mtfsb0[Rc] [FPSCRD]
```

## Encoding

### `mtfsb0x` — form `X`

- **Opcode word:** `0xfc00008c`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `70`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FPSCRD` | mtfsb0x: write | FPSCR destination field. |
| `CR` | mtfsb0x: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `mtfsb0x`

- **Reads (always):** _none_
- **Reads (conditional):** _none_
- **Writes (always):** `FPSCRD`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `mtfsb0x`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`mtfsb0x`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtfsb0x"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:406`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L406)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:179`](../../../crates/sylpheed-ppc/src/opcode.rs#L179)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1020`](../../../crates/sylpheed-ppc/src/decoder.rs#L1020)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_mtfsb0x(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}
```
</details>

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## Special Cases & Edge Conditions

- **Operation.** Clears (sets to 0) **a single named bit** of the 32-bit FPSCR. The bit is selected by `FPSCRD` (a 5-bit absolute index 0..31, big-endian: 0 = MSB = FX).
- **The mnemonic name "Bit 0" is misleading.** "0" refers to the *value being written*, not to bit position 0. Pair with [`mtfsb1x`](mtfsb1x.md) which writes a 1.
- **Restricted bits.** Per PowerISA, `mtfsb0` cannot clear bits 1 (FEX) or 2 (VX) — those are summary bits, derived from other FPSCR bits. ⚠️ Canary does not implement `mtfsb0`: its emitter is `XEINSTRNOTIMPLEMENTED`, so translating one logs "Unimplemented instr" and, with the default `break_on_unimplemented_instructions`, breaks.
- **`Rc=1`.** `mtfsb0.` (`Rc=1`) updates **CR1** with the high four FPSCR bits (FX, FEX, VX, OX) after the clear. This is the FPU's record-form analogue.
- **Common use.** Reset a sticky exception bit ahead of a sequence of FP ops you want to monitor (e.g. `mtfsb0 5` to clear ZX before a divide series, then read it back).
- **Canary status.** With `mtfsb0` unimplemented, Canary never clears the bit (and breaks by default, see above). Most FP instructions in Canary do not update FPSCR exception bits either, so titles that manage rounding only through `mtfsf`/`mtfsfi` are unaffected.
- **Not synchronising.** Reorderable.

## Related Instructions

- [`mtfsb1x`](mtfsb1x.md) — set a single FPSCR bit to 1.
- [`mtfsfx`](mtfsfx.md) — write fields of FPSCR from an FPR.
- [`mtfsfix`](mtfsfix.md) — write a 4-bit immediate into one FPSCR field.
- [`mffsx`](mffsx.md) — read FPSCR.
- [`mcrfs`](mcrfs.md) — copy FPSCR field → CR field (and clear sticky bits).

`mtfsb0` is itself the simplified form (`Rc=0`); `mtfsb0.` is the recording variant.

## IBM Reference

- [AIX 7.3 — `mtfsb0` (Move to FPSCR Bit 0)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mtfsb0-move-fpscr-bit-0-instruction)
- PowerISA v2.07B, Book I §4.6 — FPSCR bit definitions and the FX/FEX/VX restriction.