# `mtfsfx` — Move to FPSCR Fields
> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [XFL](../forms/XFL.md) · **Opcode:** `0xfc00058e`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `mtfsf` | `mtfsfx` | — | Move to FPSCR Fields |
| `mtfsf.` | `mtfsfx` | Rc=1 | Move to FPSCR Fields |
## Syntax
```asm
mtfsf[Rc] [FM], [FB]
```
## Encoding
### `mtfsfx` — form `XFL`
- **Opcode word:** `0xfc00058e`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `711`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (63) |
| 6 | `L` | field-select behaviour |
| 7–14 | `FM` | FPSCR field mask |
| 15 | `W` | immediate-value flag |
| 16–20 | `FRB` | source FPR |
| 21–30 | `XO` | extended opcode |
| 31 | `Rc` | record-form flag (updates CR1) |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `FM` | mtfsfx: read | 8-bit FPSCR field-mask used by `mtfsf`. |
| `FB` | mtfsfx: read | Source B floating-point register. |
| `FPSCR` | mtfsfx: write | Floating-Point Status and Control Register. |
| `CR` | mtfsfx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
## Register Effects
### `mtfsfx`
- **Reads (always):** `FM`, `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FPSCR`
- **Writes (conditional):** `CR`
## Status-Register Effects
- `mtfsfx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`mtfsfx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtfsfx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:416`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L416)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:182`](../../../crates/sylpheed-ppc/src/opcode.rs#L182)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1026`](../../../crates/sylpheed-ppc/src/decoder.rs#L1026)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_mtfsfx(PPCHIRBuilder& f, const InstrData& i) {
if (i.XFL.L) {
// Move/shift.
f.StoreFPSCR(
f.Truncate(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE), INT32_TYPE));
return 1;
} else {
assert_zero(i.XFL.W);
// Store under control of mask.
// Expand the mask from 8 bits -> 32 bits.
uint32_t mask = 0;
for (int j = 0; j < 8; j++) {
if (i.XFL.FM & (1 << (j ^ 7))) {
mask |= 0xF << (4 * j);
}
}
Value* v = f.Truncate(f.Cast(f.LoadFPR(i.XFL.RB), INT64_TYPE), INT32_TYPE);
if (mask != 0xFFFFFFFF) {
Value* fpscr = f.LoadFPSCR();
v = f.And(v, f.LoadConstantInt32(mask));
v = f.Or(v, f.And(fpscr, f.LoadConstantInt32(~mask)));
}
f.StoreFPSCR(v);
// Update the system rounding mode.
if (mask & 0x7) {
f.SetRoundingMode(f.And(v, f.LoadConstantInt32(7)));
}
}
if (i.XFL.Rc) {
f.CopyFPSCRToCR1();
}
return 0;
}
```