# `mtmsrd` — Move to Machine State Register Doubleword

> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c000164` · _sync_

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `mtmsrd` | `mtmsrd` | — | Move to Machine State Register Doubleword |

## Syntax

```asm
mtmsrd [RS]
```

## Encoding

### `mtmsrd` — form `X`

- **Opcode word:** `0x7c000164`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `178`
- **Synchronising:** yes

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RS` | mtmsrd: read | Source GPR (alias for RD in some stores). |
| `MSR` | mtmsrd: write | Machine State Register. |

## Register Effects

### `mtmsrd`

- **Reads (always):** `RS`
- **Reads (conditional):** _none_
- **Writes (always):** `MSR`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`mtmsrd`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtmsrd"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_control.cc:829`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_control.cc#L829)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:184`](../../../crates/sylpheed-ppc/src/opcode.rs#L184)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:900`](../../../crates/sylpheed-ppc/src/decoder.rs#L900)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_mtmsrd(PPCHIRBuilder& f, const InstrData& i) {
  // todo: this is moving msr under a mask, so only writing EE and RI

  Value* from = f.LoadGPR(i.X.RT);
  Value* mtmsrd_mask = f.LoadConstantUint64((1ULL << 15));
  Value* msr = f.LoadContext(offsetof(PPCContext, msr), INT64_TYPE);

  Value* new_msr = f.Or(f.And(from, mtmsrd_mask), f.AndNot(msr, mtmsrd_mask));

  f.StoreContext(offsetof(PPCContext, msr), new_msr);
  return 0;
}
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Privileged.** Like [`mtmsr`](mtmsr.md), supervisor-only. Game code never emits it.
- **64-bit form.** Writes all 64 MSR bits — including `MSR[SF]` (bit 0) which selects 64-bit mode, `MSR[HV]` (bit 3, hypervisor), `MSR[EE]` (32, external interrupts), `MSR[PR]` (33, problem state), `MSR[FP]` (34), `MSR[ME]` (35, machine-check enable), `MSR[DR]`/`MSR[IR]` (data/instruction translation, 38/39), `MSR[RI]` (63, recoverable interrupt). On the Xenon kernel this is the canonical MSR-write instruction.
- **`L` operand.** Same `L`-bit selector as `mtmsr`: `L=1` updates only `MSR[EE]` and `MSR[RI]`; `L=0` updates the full register. ⚠️ Canary ignores `L` and always updates **only `MSR[EE]`** (mask `0x8000`), leaving every other bit — including `RI` — unchanged.
- **Synchronisation.** Marked `sync` — execution-synchronising. PowerISA recommends `isync` afterwards if subsequent fetch / data semantics depend on the new MSR.
- **Canary model.** Not shared with `mtmsr`: `mtmsrd` computes `(RS & 0x8000) | (MSR & ~0x8000)`. No architectural side effects beyond writing the storage; no privilege check.
- **No CR / XER updates.**
- **Used in interrupt return paths.** Kernel handlers commonly write SRR1 (saved MSR) into MSR via `mtmsrd` followed by `rfid` to atomically restore state and jump to SRR0.

## Related Instructions

- [`mfmsr`](mfmsr.md) — read MSR.
- [`mtmsr`](mtmsr.md) — 32-bit form (low half only).
- [`sc`](../branch/sc.md) — kernel entry; the kernel typically pairs `mtmsrd` + `rfid` to return.

`mtmsrd` has no simplified mnemonics.

## IBM Reference

- [AIX 7.3 — `mtmsrd` (Move to Machine State Register Doubleword)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mtmsrd-move-machine-state-register-doubleword-instruction)
- PowerISA v2.07B, Book III §4.3.1 — MSR field definitions, `L`-bit semantics, and 64-bit-mode rules.