# `dcbst` — Data Cache Block Store

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00006c`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `dcbst` | `dcbst` | — | Data Cache Block Store |

## Syntax

```asm
dcbst [RA0], [RB]
```

## Encoding

### `dcbst` — form `X`

- **Opcode word:** `0x7c00006c`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `54`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | dcbst: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | dcbst: read | Source GPR. |

## Register Effects

### `dcbst`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`dcbst`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="dcbst"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1134`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1134)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:46`](../../../crates/sylpheed-ppc/src/opcode.rs#L46)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:880`](../../../crates/sylpheed-ppc/src/decoder.rs#L880)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_dcbst(PPCHIRBuilder& f, const InstrData& i) {
  if (!cvars::disable_prefetch_and_cachecontrol) {
    Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
    f.CacheControl(ea, 128, CacheControlType::CACHE_CONTROL_TYPE_DATA_STORE);
  }
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Write-through, no invalidate.** If the addressed line is dirty, it is written back to memory; the line itself remains in the cache (clean afterwards). Lighter than `dcbf` — the cache stays warm.
- **Cache line size.** Xenon's line is 128 bytes; the low seven bits of `EA` are ignored. There is no `dcbst128`; the operation is sized to the architectural line.
- **`RA0` semantics.** `RA = 0` selects literal zero as base. `dcbst 0, RB` pushes the line containing address `RB` to memory.
- **Self-modifying code stage 1.** The canonical "patch then run" sequence is `stw` (modify) → `dcbst` (push dirty data to memory) → [`sync`](../alu/sync.md) → [`icbi`](icbi.md) (invalidate I-cache for the same address) → [`isync`](../alu/isync.md). `dcbst` is preferred over `dcbf` here because it leaves the data in D-cache for any subsequent normal reads.
- **DMA hand-off.** Used before initiating a GPU or DMA read of a buffer the CPU has just written, to ensure memory holds the latest data.
- **Unprivileged.** Available from problem state.
- **Canary emits a host hint only.** No cache state is simulated: unless the `disable_prefetch_and_cachecontrol` cvar is set, `dcbst` becomes a host `clflush` over the 128-byte cache line, and memory is already authoritative.

## Related Instructions

- [`dcbf`](dcbf.md) — flush + invalidate (heavier alternative).
- [`dcbi`](dcbi.md) — invalidate without write-back (privileged).
- [`dcbz`](dcbz.md), `dcbz128` — allocate-and-zero.
- [`dcbt`](dcbt.md), [`dcbtst`](dcbtst.md) — prefetch hints.
- [`icbi`](icbi.md) — instruction-cache invalidate, sequenced after `dcbst` in self-modifying-code recipes.
- [`sync`](../alu/sync.md), [`isync`](../alu/isync.md) — ordering primitives that bracket cache control.

## IBM Reference

- [AIX 7.3 — `dcbst` (Data Cache Block Store)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-dcbst-data-cache-block-store-instruction)
- `PowerISA v2.07B Book II` § "Storage Control Instructions".