# `icbi` — Instruction Cache Block Invalidate

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0007ac`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `icbi` | `icbi` | — | Instruction Cache Block Invalidate |

## Syntax

```asm
icbi [RA], [RB]
```

## Encoding

### `icbi` — form `X`

- **Opcode word:** `0x7c0007ac`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `982`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA0` | icbi: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | icbi: read | Source GPR. |

## Register Effects

### `icbi`

- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`icbi`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="icbi"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:1179`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L1179)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:98`](../../../crates/sylpheed-ppc/src/opcode.rs#L98)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:965`](../../../crates/sylpheed-ppc/src/decoder.rs#L965)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_icbi(PPCHIRBuilder& f, const InstrData& i) {
  // XEINSTRNOTIMPLEMENTED();
  f.Nop();
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Self-modifying code primitive.** Removes the line containing `EA` from the instruction cache so a subsequent fetch reads from memory. Required after writing new instructions because the I-cache is not coherent with the D-cache or with main memory.
- **Standard recipe.** The full sequence is: `stw` (write new code) → [`dcbst`](dcbst.md) (push dirty data through D-cache to memory) → [`sync`](../alu/sync.md) (wait for memory) → `icbi` (drop stale I-cache line) → [`isync`](../alu/isync.md) (drain prefetch / refetch). Skipping any of these can leave the CPU executing stale instructions.
- **Cache line size.** Xenon's I-cache line is 128 bytes; the low seven bits of `EA` are ignored.
- **`RA0` semantics.** When `RA = 0`, base is the literal zero. `icbi 0, RB` invalidates the line containing address `RB`.
- **Unprivileged.** `icbi` is problem-state, unlike its data-side cousin [`dcbi`](dcbi.md).
- **No exception on bad address.** Treated as a hint at the hardware level — invalidating an absent line is harmless.
- **Per-thread effect.** On the multithreaded Xenon core, `icbi` propagates across hardware threads sharing the same L1 I-cache; cross-core invalidation requires bus broadcast handled implicitly by the cache coherence protocol.
- **Canary emits a no-op.** No I-cache is simulated; Canary's `icbi` emitter is a `Nop`.

## Related Instructions

- [`dcbst`](dcbst.md) — D-cache write-back (paired step before `icbi`).
- [`dcbf`](dcbf.md), [`dcbi`](dcbi.md) — D-cache push / invalidate.
- [`isync`](../alu/isync.md) — instruction-stream barrier (paired step after `icbi`).
- [`sync`](../alu/sync.md) — full memory barrier between `dcbst` and `icbi`.

## IBM Reference

- [AIX 7.3 — `icbi` (Instruction Cache Block Invalidate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-icbi-instruction-cache-block-invalidate-instruction)
- `PowerISA v2.07B Book II` § "Instruction Storage" for the canonical self-modifying-code sequence.