# `ld` — Load Doubleword
> **Category:** [Memory](../categories/memory.md) · **Form:** [DS](../forms/DS.md) · **Opcode:** `0xe8000000`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `ld` | `ld` | — | Load Doubleword |
| `ldu` | `ldu` | — | Load Doubleword with Update |
| `ldux` | `ldux` | — | Load Doubleword with Update Indexed |
| `ldx` | `ldx` | — | Load Doubleword Indexed |
## Syntax
```asm
ld [RD], [ds]([RA0])
ldu [RD], [ds]([RA])
ldux [RD], [RA], [RB]
ldx [RD], [RA0], [RB]
```
## Encoding
### `ld` — form `DS`
- **Opcode word:** `0xe8000000`
- **Primary opcode (bits 0–5):** `58`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
### `ldu` — form `DS`
- **Opcode word:** `0xe8000001`
- **Primary opcode (bits 0–5):** `58`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0) |
| 16–29 | `DS` | 14-bit signed word-scaled displacement |
| 30–31 | `XO` | extended opcode |
### `ldux` — form `X`
- **Opcode word:** `0x7c00006a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `53`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `ldx` — form `X`
- **Opcode word:** `0x7c00002a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `21`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RA0` | ld: read; ldx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `ds` | ld: read; ldu: read | 14-bit signed word-aligned displacement (`DS << 2`). |
| `RD` | ld: write; ldu: write; ldux: write; ldx: write | Destination GPR. |
| `RA` | ldu: read; ldu: write; ldux: read; ldux: write | Source GPR (`r0`–`r31`). |
| `RB` | ldux: read; ldx: read | Source GPR. |
## Register Effects
### `ld`
- **Reads (always):** `RA0`, `ds`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_
### `ldu`
- **Reads (always):** `RA`, `ds`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `RA`
- **Writes (conditional):** _none_
### `ldux`
- **Reads (always):** `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`, `RA`
- **Writes (conditional):** _none_
### `ldx`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- (RA|0) + EXTS(ds || 0b00)
RT <- MEM(EA, 8)
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`ld`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="ld"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:347`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L347)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:106`](../../../crates/sylpheed-ppc/src/opcode.rs#L106)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:495`](../../../crates/sylpheed-ppc/src/decoder.rs#L495)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_ld(PPCHIRBuilder& f, const InstrData& i) {
// if RA = 0 then
// b <- 0
// else
// b <- (RA)
// EA <- b + EXTS(DS || 0b00)
// RT <- MEM(EA, 8)
Value* b;
if (i.DS.RA == 0) {
b = f.LoadZeroInt64();
} else {
b = f.LoadGPR(i.DS.RA);
}
Value* offset = f.LoadConstantInt64(XEEXTS16(i.DS.DS << 2));
Value* rt = f.ByteSwap(f.LoadOffset(b, offset, INT64_TYPE));
f.StoreGPR(i.DS.RT, rt);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_ldu(PPCHIRBuilder& f, const InstrData& i) {
// EA <- (RA) + EXTS(DS || 0b00)
// RT <- MEM(EA, 8)
// RA <- EA
Value* ea = CalculateEA_i(f, i.DS.RA, XEEXTS16(i.DS.DS << 2));
Value* rt = f.ByteSwap(f.Load(ea, INT64_TYPE));
f.StoreGPR(i.DS.RT, rt);
StoreEA(f, i.DS.RA, ea);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_ldux(PPCHIRBuilder& f, const InstrData& i) {
// EA <- (RA) + (RB)
// RT <- MEM(EA, 8)
// RA <- EA
Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
Value* rt = f.ByteSwap(f.Load(ea, INT64_TYPE));
f.StoreGPR(i.X.RT, rt);
StoreEA(f, i.X.RA, ea);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_ldx(PPCHIRBuilder& f, const InstrData& i) {
// if RA = 0 then
// b <- 0
// else
// b <- (RA)
// EA <- b + (RB)
// RT <- MEM(EA, 8)
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
Value* rt = f.ByteSwap(f.Load(ea, INT64_TYPE));
f.StoreGPR(i.X.RT, rt);
return 0;
}
```