# `lvx` — Load Vector Indexed
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0000ce`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lvx` | `lvx` | — | Load Vector Indexed |
| `lvx128` | `lvx128` | — | Load Vector Indexed 128 |
## Syntax
```asm
lvx [VD], [RA0], [RB]
lvx128 [VD], [RA0], [RB]
```
## Encoding
### `lvx` — form `X`
- **Opcode word:** `0x7c0000ce`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `103`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `lvx128` — form `VX128_1`
- **Opcode word:** `0x100000c3`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `195`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RA0` | lvx: read; lvx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | lvx: read; lvx128: read | Source GPR. |
| `VD` | lvx: write; lvx128: write | Destination vector register. |
## Register Effects
### `lvx`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `lvx128`
- **Reads (always):** `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- ((RA|0) + (RB)) & ~0xF ; align to 16
VD <- byteswap(MEM(EA, 16))
```
## C Translation Example
```c
/* lvx VD, RA, RB — 16-byte aligned load of a vector register */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
uint32_t ea = (uint32_t)((base + r[insn.RB]) & ~(uint64_t)0xF);
v[insn.VD] = mem_read_vec128_be(ea);
```
## Implementation References
**`lvx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lvx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:139`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L139)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:152`](../../../crates/sylpheed-ppc/src/opcode.rs#L152)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:890`](../../../crates/sylpheed-ppc/src/decoder.rs#L890)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_lvx(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_lvx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:133) ──
int InstrEmit_lvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantInt64(~0xFull));
f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_lvx128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_lvx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:133) ──
int InstrEmit_lvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantInt64(~0xFull));
f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
return 0;
}
```