# `stmw` — Store Multiple Word

> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xbc000000`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stmw` | `stmw` | — | Store Multiple Word |

## Syntax

```asm
(no disassembly template)
```

## Encoding

### `stmw` — form `D`

- **Opcode word:** `0xbc000000`
- **Primary opcode (bits 0–5):** `47`
- **Extended opcode:** —
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |

## Operands

| Field | Role | Description |
| --- | --- | --- |

## Register Effects

### `stmw`

- **Reads (always):** _none_
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`stmw`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stmw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:527`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L527)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:253`](../../../crates/sylpheed-ppc/src/opcode.rs#L253)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:485`](../../../crates/sylpheed-ppc/src/decoder.rs#L485)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_stmw(PPCHIRBuilder& f, const InstrData& i) {
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  for (uint32_t j = 0; j < 32 - i.D.RT; ++j) {
    Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS) + j * 4);
    f.StoreOffset(b, offset,
                  f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT + j), INT32_TYPE)));
  }
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Bulk register save.** Stores `(32 - RS)` consecutive 32-bit words taken from `r[RS]`, `r[RS+1]`, …, `r31` to memory starting at `EA`. The symmetric counterpart of [`lmw`](lmw.md). Used by AIX/PowerPC ABI prologues to save non-volatile GPRs in one instruction.
- **Each store is the low 32 bits of the GPR.** Canary stores `ByteSwap(Truncate(GPR, INT32))` for each register — only the low half of the 64-bit GPR. The high 32 bits are discarded; `stmw` cannot save 64-bit values (use a sequence of [`std`](std.md) instead).
- **Big-endian write.** Word from `r[RS]` lands at `EA`, word from `r[RS+1]` at `EA+4`, etc. Each word is itself written most-significant-byte first.
- **`RA0` semantics.** When `RA = 0`, base is the literal zero. Useful for absolute-address restoration.
- **Alignment.** PowerISA requires word-aligned `EA`; an unaligned `stmw` may raise an alignment exception on hardware. Canary does not check.
- **Performance trap.** Modern PowerPC implementations microcode `stmw` — typically slower than the same number of `stw` instructions. Compilers prefer the unrolled form.
- **Cache-line behaviour.** When the run of words crosses several 128-byte cache lines, each cold line triggers a read-allocate. Pre-clearing with [`dcbz128`](dcbz.md) helps for fresh frames.

## Related Instructions

- [`lmw`](lmw.md) — symmetric "load multiple words" (the matching epilogue partner).
- [`stw`](stw.md), [`stwx`](stw.md) — single-word stores; the modern preferred form.
- [`stswi`](stswi.md), [`stswx`](stswx.md) — store string (byte-granular bulk transfer).
- [`std`](std.md) — for 64-bit values (no "store multiple doubleword" exists).

## IBM Reference

- [AIX 7.3 — `stmw` (Store Multiple Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stmw-store-multiple-word-instruction)
- `PowerISA v2.07B Book II` § "Load and Store Multiple".