# `stswi` — Store String Word Immediate

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0005aa`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stswi` | `stswi` | — | Store String Word Immediate |

## Syntax

```asm
(no disassembly template)
```

## Encoding

### `stswi` — form `X`

- **Opcode word:** `0x7c0005aa`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `725`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |

## Register Effects

### `stswi`

- **Reads (always):** _none_
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`stswi`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stswi"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:737`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L737)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:254`](../../../crates/sylpheed-ppc/src/opcode.rs#L254)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:950`](../../../crates/sylpheed-ppc/src/decoder.rs#L950)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_stswi(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}
```
</details>

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## Special Cases & Edge Conditions

- **Byte-granular bulk store.** Symmetric counterpart of [`lswi`](lswi.md). Reads the low 32 bits of `RS`, `RS+1`, …, takes the top byte of each (then the next, etc.) and writes successive bytes at `EA`. The byte count `NB` is in the `RB` field of the encoding (1..31), with `NB = 0` meaning "32 bytes".
- **Register wraparound at r31 → r0.** After r31 the source becomes r0, then r1, etc. Rare in practice; AIX flags overlapping register / address ranges as invalid. ⚠️ Canary does not implement `stswi`: its emitter is `XEINSTRNOTIMPLEMENTED`, so translating one logs "Unimplemented instr" and, with the default `break_on_unimplemented_instructions`, breaks.
- **Big-endian byte ordering inside each register.** Writes the most-significant byte first: `mem.write_u8(ea, (val >> 24) as u8)`, then bits 16–23, etc. Matches the byte order produced by [`lswi`](lswi.md), so a `lswi`/`stswi` pair round-trips a buffer.
- **Last partial register.** When `NB` is not a multiple of 4, the final source register has its trailing low bytes ignored — only the leading bytes that fit in the byte budget are written.
- **`RA0` semantics.** `RA = 0` selects literal zero. `stswi` is not an update form; `RA` is not modified.
- **Alignment.** Architecture allows arbitrary alignment; cache-inhibited storage may raise alignment exceptions on hardware.
- **Vanishingly rare in compiled code.** Compilers don't emit `stswi`. Hand-written `memcpy` cores may.

## Related Instructions

- [`lswi`](lswi.md) — symmetric load.
- [`stswx`](stswx.md) — register-supplied byte-count variant.
- [`stmw`](stmw.md) — word-granular bulk store.
- [`stw`](stw.md), [`stb`](stb.md) — scalar stores compilers actually emit.

## IBM Reference

- [AIX 7.3 — `stswi` (Store String Word Immediate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-stswi-store-string-word-immediate-instruction)
- `PowerISA v2.07B Book II` § "Load and Store String".