# `stvx` — Store Vector Indexed
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0001ce`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stvx` | `stvx` | — | Store Vector Indexed |
| `stvx128` | `stvx128` | — | Store Vector Indexed 128 |
## Syntax
```asm
stvx [VS], [RA0], [RB]
stvx128 [VS], [RA0], [RB]
```
## Encoding
### `stvx` — form `X`
- **Opcode word:** `0x7c0001ce`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `231`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `stvx128` — form `VX128_1`
- **Opcode word:** `0x100001c3`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `451`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VS` | stvx: read; stvx128: read | Source vector register (alias for VD on stores). |
| `RA0` | stvx: read; stvx128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stvx: read; stvx128: read | Source GPR. |
## Register Effects
### `stvx`
- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
### `stvx128`
- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- ((RA|0) + (RB)) & ~0xF ; align to 16
MEM(EA, 16) <- byteswap(VS)
```
## C Translation Example
```c
/* stvx VS, RA, RB — 16-byte aligned store of a vector register */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
uint32_t ea = (uint32_t)((base + r[insn.RB]) & ~(uint64_t)0xF);
mem_write_vec128_be(ea, v[insn.VS]);
```
## Implementation References
**`stvx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:193`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L193)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:269`](../../../crates/sylpheed-ppc/src/opcode.rs#L269)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:906`](../../../crates/sylpheed-ppc/src/decoder.rs#L906)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stvx(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_stvx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:187) ──
int InstrEmit_stvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantUint64(~0xFull));
f.Store(ea, f.ByteSwap(f.LoadVR(vd)));
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stvx128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_stvx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:187) ──
int InstrEmit_stvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantUint64(~0xFull));
f.Store(ea, f.ByteSwap(f.LoadVR(vd)));
return 0;
}
```