# `stvxl` — Store Vector Indexed LRU
> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c0003ce`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stvxl` | `stvxl` | — | Store Vector Indexed LRU |
| `stvxl128` | `stvxl128` | — | Store Vector Indexed LRU 128 |
## Syntax
```asm
stvxl [VS], [RA0], [RB]
stvxl128 [VS], [RA0], [RB]
```
## Encoding
### `stvxl` — form `X`
- **Opcode word:** `0x7c0003ce`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `487`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `stvxl128` — form `VX128_1`
- **Opcode word:** `0x100003c3`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `963`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `RA` | address register |
| 16–20 | `RB` | offset register |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `—` | reserved |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VS` | stvxl: read; stvxl128: read | Source vector register (alias for VD on stores). |
| `RA0` | stvxl: read; stvxl128: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `RB` | stvxl: read; stvxl128: read | Source GPR. |
## Register Effects
### `stvxl`
- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
### `stvxl128`
- **Reads (always):** `VS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`stvxl`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stvxl"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:199`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L199)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:271`](../../../crates/sylpheed-ppc/src/opcode.rs#L271)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:928`](../../../crates/sylpheed-ppc/src/decoder.rs#L928)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stvxl(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_stvx(f, i);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:193) ──
int InstrEmit_stvx(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_stvx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:187) ──
int InstrEmit_stvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantUint64(~0xFull));
f.Store(ea, f.ByteSwap(f.LoadVR(vd)));
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stvxl128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_stvx128(f, i);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:196) ──
int InstrEmit_stvx128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_stvx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:187) ──
int InstrEmit_stvx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
uint32_t ra, uint32_t rb) {
Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstantUint64(~0xFull));
f.Store(ea, f.ByteSwap(f.LoadVR(vd)));
return 0;
}
```