# `vpkpx` — Vector Pack Pixel

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000030e`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vpkp` | `vpkpx` | — | Vector Pack Pixel |

## Syntax

```asm
vpkpx [VD], [VA], [VB]
```

## Encoding

### `vpkpx` — form `VX`

- **Opcode word:** `0x1000030e`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `782`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vpkpx: read | Source A vector register. |
| `VB` | vpkpx: read | Source B vector register. |
| `VD` | vpkpx: write | Destination vector register. |

## Register Effects

### `vpkpx`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vpkpx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vpkpx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1796`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1796)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:404`](../../../crates/sylpheed-ppc/src/opcode.rs#L404)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:619`](../../../crates/sylpheed-ppc/src/decoder.rs#L619)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vpkpx(PPCHIRBuilder& f, const InstrData& i) {
  // I compared the results of this against over a million randomly generated
  // sets of inputs and all compared equal

  Value* src1 = f.LoadVR(i.VX.VA);

  Value* src2 = f.LoadVR(i.VX.VB);

  Value* pck1 = vkpkx_in_low(f, src1);
  Value* pck2 = vkpkx_in_low(f, src2);

  Value* result = f.Pack(
      pck1, pck2,
      PACK_TYPE_16_IN_32 | PACK_TYPE_IN_UNSIGNED | PACK_TYPE_OUT_UNSIGNED);

  f.StoreVR(i.VX.VD, result);

  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Pack 4×4 pixel words → 8×16-bit 1-5-5-5 pixels.** For each 32-bit word lane, three bit-fields are sampled and concatenated into a 16-bit `1.5.5.5` (A.R.G.B) format, losing precision but not saturating.
- **Bit-layout of each output half-word.** Bit 0 of the output = bit 7 of the source byte (alpha); the next 5 bits come from the red channel's top 5 bits (bits 8..12 of the source word); then 5 bits of green (bits 16..20); then 5 bits of blue (bits 24..28). Canary builds it with `vkpkx_in_low` plus an unsigned 32→16 `Pack`; its comment reports agreement over a million random inputs.
- **No saturation / no rounding.** The op truncates the lower bits of each channel; `VSCR[SAT]` is **not** affected.
- **Big-endian lane order.** `VA`'s 4 words produce the first 4 output half-words (`VD.h[0..3]`); `VB`'s 4 words fill `VD.h[4..7]`.
- **Paired with [`vupkhpx`](vupkhpx.md) / [`vupklpx`](vupklpx.md)** — these unpack a 1-5-5-5 pixel back into a word-lane `0x00RRGGBB`-like form for further arithmetic.
- **No `Rc`, no XER.** No VMX128 sibling — game code that needs 555-pixel packing on Xenon either uses the scalar path or runs into the `vpkd3d128` family for richer D3D formats.

## Related Instructions

- [`vupkhpx`](vupkhpx.md), [`vupklpx`](vupklpx.md) — the inverse unpacks.
- [`vpkuhum`](vpkuhum.md), [`vpkuhus`](vpkuhus.md), [`vpkuwum`](vpkuwum.md), [`vpkuwus`](vpkuwus.md) — lane-halving packs (unsigned modulo / saturating).
- [`vpkshss`](vpkshss.md), [`vpkshus`](vpkshus.md), [`vpkswss`](vpkswss.md), [`vpkswus`](vpkswus.md) — signed-input saturating packs.
- [`vpkd3d128`](../vmx128/vpkd3d128.md) — VMX128-exclusive D3D-format pack (richer pixel formats than 1-5-5-5).

## IBM Reference

- [AIX 7.3 — `vpkpx` (Vector Pack Pixel32)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vpkpx-vector-pack-pixel32-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Permute and Formatting](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)