# `vspltisw` — Vector Splat Immediate Signed Word
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000038c`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vspltisw` | `vspltisw` | — | Vector Splat Immediate Signed Word |
| `vspltisw128` | `vspltisw128` | — | Vector128 Splat Immediate Signed Word |
## Syntax
```asm
vspltisw [VD], [SIMM]
vspltisw128 [VD], [SIMM]
```
## Encoding
### `vspltisw` — form `VX`
- **Opcode word:** `0x1000038c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `908`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
### `vspltisw128` — form `VX128_3`
- **Opcode word:** `0x18000770`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `1904`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `SIMM` | vspltisw: read; vspltisw128: read | 16-bit signed immediate. Sign-extended to 64 bits before use. |
| `VD` | vspltisw: write; vspltisw128: write | Destination vector register. |
## Register Effects
### `vspltisw`
- **Reads (always):** `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `vspltisw128`
- **Reads (always):** `SIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vspltisw`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltisw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1566`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1566)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:453`](../../../crates/sylpheed-ppc/src/opcode.rs#L453)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:631`](../../../crates/sylpheed-ppc/src/decoder.rs#L631)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_vspltisw(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vspltisw_(f, i.VX.VD, i.VX.VA);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1552) ──
int InstrEmit_vspltisw_(PPCHIRBuilder& f, uint32_t vd, uint32_t uimm) {
// (VD.xyzw) <- sign_extend(uimm)
Value* v;
if (uimm) {
// Sign extend from 5bits -> 32 and load.
int32_t simm = (uimm & 0x10) ? (uimm | 0xFFFFFFF0) : uimm;
v = f.Splat(f.LoadConstantInt32(simm), VEC128_TYPE);
} else {
// Zero out the register.
v = f.LoadZeroVec128();
}
f.StoreVR(vd, v);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_vspltisw128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vspltisw_(f, VX128_3_VD128, VX128_3_IMM);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1552) ──
int InstrEmit_vspltisw_(PPCHIRBuilder& f, uint32_t vd, uint32_t uimm) {
// (VD.xyzw) <- sign_extend(uimm)
Value* v;
if (uimm) {
// Sign extend from 5bits -> 32 and load.
int32_t simm = (uimm & 0x10) ? (uimm | 0xFFFFFFF0) : uimm;
v = f.Splat(f.LoadConstantInt32(simm), VEC128_TYPE);
} else {
// Zero out the register.
v = f.LoadZeroVec128();
}
f.StoreVR(vd, v);
return 0;
}
```