# `fmulx` — Floating Multiply

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc000032`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fmul` | `fmulx` | — | Floating Multiply |
| `fmul.` | `fmulx` | Rc=1 | Floating Multiply |

## Syntax

```asm
fmul[Rc] [FD], [FA], [FC]
```

## Encoding

### `fmulx` — form `A`

- **Opcode word:** `0xfc000032`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `25`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (59 or 63) |
| 6–10 | `FRT` | destination FPR |
| 11–15 | `FRA` | source A FPR |
| 16–20 | `FRB` | source B FPR |
| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
| 26–30 | `XO` | extended opcode (5 bits) |
| 31 | `Rc` | record-form flag (updates CR1) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FA` | fmulx: read | Source A floating-point register (`fr0`–`fr31`). |
| `FC` | fmulx: read | Source C floating-point register (for madd-style ops). |
| `FD` | fmulx: write | Destination floating-point register. |
| `CR` | fmulx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | fmulx: write | Floating-Point Status and Control Register. |

## Register Effects

### `fmulx`

- **Reads (always):** `FA`, `FC`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fmulx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
FRT <- FRA × FRC
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fmulx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fmulx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:89`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L89)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:82`](../../../crates/sylpheed-ppc/src/opcode.rs#L82)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1040`](../../../crates/sylpheed-ppc/src/decoder.rs#L1040)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_fmulx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- (frA) x (frC)
  Value* v = f.Mul(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRC));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **A-form quirk: multiplier is `FRC`, not `FRB`.** `fmul` reads operands from the `FRA` (bits 11–15) and `FRC` (bits 21–25) fields, bridging the multiply and fused-multiply-add families. Canary reads the multiplier from `i.A.FRC` (distinct from the record bit `Rc`).
- **Double precision.** Operates on IEEE-754 binary64; [`fmulsx`](fmulsx.md) rounds to binary32.
- **`0 × ±∞` is invalid.** Sets `FPSCR[VXIMZ, VX, FX]` and yields a quiet NaN.
- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX` plus exception bits `OX` (overflow), `UX` (underflow), `XX` (inexact), `VXIMZ` (0×∞), `VXSNAN` (signalling NaN). Canary does **not** update FPSCR (`UpdateFPSCR` is a stub).
- **`Rc=1` (`fmul.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **NaN propagation.** Any NaN operand yields a quiet NaN; signalling NaNs are quietened.
- **Sign of result.** Standard IEEE: `sign(a) XOR sign(c)`. `+0 × −0 = −0` and `−x × +∞ = −∞`.
- **Denormal flush.** That Xenon boots with `FPSCR[NI]=1` is unverified. Canary starts every guest thread in IEEE mode (MXCSR `0x1F80`; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (`MXCSR.FZ`) only when the guest sets `NI` through `mtfsf`/`mtfsfi`.
- **Rounding mode** uses `FPSCR[RN]` (default nearest-even).

## Related Instructions

- [`fmulsx`](fmulsx.md) — single-precision multiply.
- [`fmaddx`](fmaddx.md), [`fmsubx`](fmsubx.md), [`fnmaddx`](fnmaddx.md), [`fnmsubx`](fnmsubx.md) — fused multiply-add family; share the same `FRA × FRC` core but add/subtract `FRB` with a single rounding step. Prefer fused forms for dot products and polynomial evaluation.
- [`faddx`](faddx.md), [`fsubx`](fsubx.md), [`fdivx`](fdivx.md) — sibling double-precision arithmetic.
- [`fresx`](fresx.md), [`frsqrtex`](frsqrtex.md) — reciprocal helpers commonly paired with `fmul` for reciprocal divides.
- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR control.

## IBM Reference

- [AIX 7.3 — `fmul` (Floating Multiply)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fm-fmul-floating-multiply-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/).