# `frsqrtex` — Floating Reciprocal Square Root Estimate

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc000034`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `frsqrte` | `frsqrtex` | — | Floating Reciprocal Square Root Estimate |
| `frsqrte.` | `frsqrtex` | Rc=1 | Floating Reciprocal Square Root Estimate |

## Syntax

```asm
frsqrte[Rc] [FD], [FB]
```

## Encoding

### `frsqrtex` — form `A`

- **Opcode word:** `0xfc000034`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `26`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (59 or 63) |
| 6–10 | `FRT` | destination FPR |
| 11–15 | `FRA` | source A FPR |
| 16–20 | `FRB` | source B FPR |
| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
| 26–30 | `XO` | extended opcode (5 bits) |
| 31 | `Rc` | record-form flag (updates CR1) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FB` | frsqrtex: read | Source B floating-point register. |
| `FD` | frsqrtex: write | Destination floating-point register. |
| `CR` | frsqrtex: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | frsqrtex: write | Floating-Point Status and Control Register. |

## Register Effects

### `frsqrtex`

- **Reads (always):** `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `frsqrtex`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`frsqrtex`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="frsqrtex"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:118`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L118)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:91`](../../../crates/sylpheed-ppc/src/opcode.rs#L91)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1041`](../../../crates/sylpheed-ppc/src/decoder.rs#L1041)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_frsqrtex(PPCHIRBuilder& f, const InstrData& i) {
  // Double precision:
  // frD <- 1/sqrt(frB)
  Value* v = f.RSqrt(f.LoadFPR(i.A.FRB));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Reciprocal-square-root estimate.** PowerISA: a low-precision estimate of `1/sqrt(FRB)`, correct to one part in 32, designed as the seed for Newton-Raphson refinement. Canary's x64 backend also returns a low-precision estimate rather than the exact value: `frsqrtefp_helper` takes an 8-bit significand from a 16-entry table indexed by the exponent's parity and the top three significand bits. Whether that matches Xenon bit-for-bit is unverified.
- **Double precision result.** Per PowerISA, `frsqrte` returns a binary64 estimate (not a single-rounded value, unlike `fres`).
- **Negative input is invalid.** `frsqrte(x < 0)` (other than `-0`) sets `FPSCR[VXSQRT, VX, FX]` and yields a quiet NaN. Canary's helper returns the default quiet NaN `0x7FF8_0000_0000_0000` but does not raise the FPSCR bit.
- **`frsqrte(+0) = +∞`** and sets `FPSCR[ZX]` per spec. **`frsqrte(-0) = -∞`**.
- **`frsqrte(+∞) = +0`**.
- **NaN propagation.** Quiet NaN; signalling NaNs are quietened.
- **`Rc=1` (`frsqrte.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **Encoding.** A-form, primary 63, XO 26. Reads `FRB` only; `FRA`/`FRC` are don't-care.
- **Use case.** The canonical `length`/`normalize` recipe: `inv_len = frsqrte(dot); inv_len = 0.5 * inv_len * (3 - dot * inv_len * inv_len);` — one NR step gets to full double precision. For single precision use `frsp` after.
- **Performance.** Cheap on Xenon. The `length`/`normalize` macro built on `frsqrte` is the hot inner loop in any 3D Xbox 360 game.

## Related Instructions

- [`fresx`](fresx.md) — reciprocal estimate; same NR-refinement design pattern.
- [`fsqrtx`](fsqrtx.md), [`fsqrtsx`](fsqrtsx.md) — full-precision square root (multi-cycle, non-pipelined).
- [`fmulx`](fmulx.md), [`fmaddx`](fmaddx.md), [`fnmsubx`](fnmsubx.md) — the multiply/FMA ops that drive NR refinement.
- [`frspx`](frspx.md) — round to single after `frsqrte` for graphics-pipeline producers expecting `float`.

## IBM Reference

- [AIX 7.3 — `frsqrte` (Floating Reciprocal Square Root Estimate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-frsqrte-floating-reciprocal-square-root-estimate-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (relative-error bound for `frsqrte`; canonical NR refinement step).