# `lfd` — Load Floating-Point Double > **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xc8000000` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `lfd` | `lfd` | — | Load Floating-Point Double | | `lfdu` | `lfdu` | — | Load Floating-Point Double with Update | | `lfdux` | `lfdux` | — | Load Floating-Point Double with Update Indexed | | `lfdx` | `lfdx` | — | Load Floating-Point Double Indexed | ## Syntax ```asm lfd [FD], [d]([RA0]) lfdu [FD], [d]([RA]) lfdux [FD], [RA], [RB] lfdx [FD], [RA0], [RB] ``` ## Encoding ### `lfd` — form `D` - **Opcode word:** `0xc8000000` - **Primary opcode (bits 0–5):** `50` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `lfdu` — form `D` - **Opcode word:** `0xcc000000` - **Primary opcode (bits 0–5):** `51` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `lfdux` — form `X` - **Opcode word:** `0x7c0004ee` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `631` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ### `lfdx` — form `X` - **Opcode word:** `0x7c0004ae` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `599` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ## Operands | Field | Role | Description | | --- | --- | --- | | `RA0` | lfd: read; lfdx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. | | `d` | lfd: read; lfdu: read | 16-bit signed displacement (`d`) added to the base address register. | | `FD` | lfd: write; lfdu: write; lfdux: write; lfdx: write | Destination floating-point register. | | `RA` | lfdu: read; lfdu: write; lfdux: read; lfdux: write | Source GPR (`r0`–`r31`). | | `RB` | lfdux: read; lfdx: read | Source GPR. | ## Register Effects ### `lfd` - **Reads (always):** `RA0`, `d` - **Reads (conditional):** _none_ - **Writes (always):** `FD` - **Writes (conditional):** _none_ ### `lfdu` - **Reads (always):** `RA`, `d` - **Reads (conditional):** _none_ - **Writes (always):** `FD`, `RA` - **Writes (conditional):** _none_ ### `lfdux` - **Reads (always):** `RA`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `FD`, `RA` - **Writes (conditional):** _none_ ### `lfdx` - **Reads (always):** `RA0`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `FD` - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` EA <- (RA|0) + EXTS(d) FRT <- MEM(EA, 8) ``` ## C Translation Example ```c /* No hand-written C yet. Translate the Canary emitter snapshot */ /* under Implementation References; its HIR maps directly: */ /* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */ /* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */ /* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */ /* wrap them in f.ByteSwap for the big-endian guest value */ /* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */ /* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */ /* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`lfd`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfd"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:912`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L912) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:113`](../../../crates/sylpheed-ppc/src/opcode.rs#L113) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:488`](../../../crates/sylpheed-ppc/src/decoder.rs#L488)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfd(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + EXTS(D) // FRT <- MEM(EA, 8) Value* ea = CalculateEA_0_i(f, i.D.RA, XEEXTS16(i.D.DS)); Value* rt = f.Cast(f.ByteSwap(f.Load(ea, INT64_TYPE)), FLOAT64_TYPE); f.StoreFPR(i.D.RT, rt); return 0; } ```
**`lfdu`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfdu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:925`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L925) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:114`](../../../crates/sylpheed-ppc/src/opcode.rs#L114) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:489`](../../../crates/sylpheed-ppc/src/decoder.rs#L489)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfdu(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + EXTS(D) // FRT <- MEM(EA, 8) // RA <- EA Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS)); Value* rt = f.Cast(f.ByteSwap(f.Load(ea, INT64_TYPE)), FLOAT64_TYPE); f.StoreFPR(i.D.RT, rt); StoreEA(f, i.D.RA, ea); return 0; } ```
**`lfdux`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfdux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:936`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L936) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:115`](../../../crates/sylpheed-ppc/src/opcode.rs#L115) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:942`](../../../crates/sylpheed-ppc/src/decoder.rs#L942)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfdux(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + (RB) // FRT <- MEM(EA, 8) // RA <- EA Value* ea = CalculateEA(f, i.X.RA, i.X.RB); Value* rt = f.Cast(f.ByteSwap(f.Load(ea, INT64_TYPE)), FLOAT64_TYPE); f.StoreFPR(i.X.RT, rt); StoreEA(f, i.X.RA, ea); return 0; } ```
**`lfdx`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfdx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:947`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L947) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:116`](../../../crates/sylpheed-ppc/src/opcode.rs#L116) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:941`](../../../crates/sylpheed-ppc/src/decoder.rs#L941)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfdx(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + (RB) // FRT <- MEM(EA, 8) Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); Value* rt = f.Cast(f.ByteSwap(f.Load(ea, INT64_TYPE)), FLOAT64_TYPE); f.StoreFPR(i.X.RT, rt); return 0; } ```
## Special Cases & Edge Conditions - **Bit-exact double load.** Reads 8 bytes and places them directly into `FRT` as IEEE-754 binary64. No format conversion is performed (contrast `lfs`, which expands single→double). - **No FPSCR side effects.** `lfd` cannot raise IEEE exceptions: it neither rounds nor inspects the value. A signalling NaN read this way stays a signalling NaN until it is consumed by an arithmetic op. - **`RA0` semantics.** In the non-update forms (`lfd`, `lfdx`), `RA = 0` selects literal zero — `lfd FT, 0(0)` loads from absolute address 0. Update forms `lfdu` / `lfdux` invoke `RA = 0` and `RA = RT` (here `RA` is GPR; `RT` is FPR, so the latter cannot collide) as invalid forms when `RA = 0`. - **Alignment.** Xenon tolerates unaligned 8-byte FP loads; PowerISA technically permits implementations to raise alignment exceptions for FP loads, so portable code uses 8-byte aligned addresses. - **Big-endian read.** Bytes are interpreted big-endian: byte at `EA` is bits 0–7 of the IEEE pattern (sign + part of exponent), byte at `EA+7` is bits 56–63 of the mantissa. Canary byte-swaps the loaded doubleword and reinterprets it as binary64 (`Cast`), bit-exact. - **MSR[FP] required.** Like all FP-register accesses, `lfd` requires the FP unit be enabled (MSR[FP]=1). Otherwise a Floating-Point Unavailable interrupt is raised. Canary does not check `MSR[FP]`. - **Pair with [`stfd`](stfd.md).** Store-double is the symmetric counterpart. ## Related Instructions - [`lfs`](lfs.md) — single-precision load with format conversion to double. - [`stfd`](stfd.md), [`stfdu`](stfd.md), [`stfdx`](stfd.md), [`stfdux`](stfd.md) — corresponding stores. - [`stfiwx`](stfiwx.md) — store-FP-as-integer-word (the asymmetric oddity in the FP load/store family). - [`ld`](ld.md) — integer doubleword load (same width, GPR target). ## IBM Reference - [AIX 7.3 — `lfd` (Load Floating-Point Double)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lfd-load-floating-point-double-instruction) - [AIX 7.3 — `lfdu` / `lfdx` / `lfdux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lfdu-load-floating-point-double-update-instruction)