# `lfs` — Load Floating-Point Single > **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0xc0000000` ## Assembler Mnemonics | Mnemonic | XML entry | Flags | Description | | --- | --- | --- | --- | | `lfs` | `lfs` | — | Load Floating-Point Single | | `lfsu` | `lfsu` | — | Load Floating-Point Single with Update | | `lfsux` | `lfsux` | — | Load Floating-Point Single with Update Indexed | | `lfsx` | `lfsx` | — | Load Floating-Point Single Indexed | ## Syntax ```asm lfs [FD], [d]([RA0]) lfsu [FD], [d]([RA]) lfsux [FD], [RA], [RB] lfsx [FD], [RA0], [RB] ``` ## Encoding ### `lfs` — form `D` - **Opcode word:** `0xc0000000` - **Primary opcode (bits 0–5):** `48` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `lfsu` — form `D` - **Opcode word:** `0xc4000000` - **Primary opcode (bits 0–5):** `49` - **Extended opcode:** — - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT` | destination GPR (or RS when storing) | | 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) | | 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate | ### `lfsux` — form `X` - **Opcode word:** `0x7c00046e` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `567` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ### `lfsx` — form `X` - **Opcode word:** `0x7c00042e` - **Primary opcode (bits 0–5):** `31` - **Extended opcode:** `535` - **Synchronising:** no | Bits | Field | Meaning | | --- | --- | --- | | 0–5 | `OPCD` | primary opcode | | 6–10 | `RT/FRT/VRT` | destination | | 11–15 | `RA/FRA/VRA` | source A | | 16–20 | `RB/FRB/VRB` | source B | | 21–30 | `XO` | extended opcode (10 bits) | | 31 | `Rc` | record-form flag | ## Operands | Field | Role | Description | | --- | --- | --- | | `RA0` | lfs: read; lfsx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. | | `d` | lfs: read; lfsu: read | 16-bit signed displacement (`d`) added to the base address register. | | `FD` | lfs: write; lfsu: write; lfsux: write; lfsx: write | Destination floating-point register. | | `RA` | lfsu: read; lfsu: write; lfsux: read; lfsux: write | Source GPR (`r0`–`r31`). | | `RB` | lfsux: read; lfsx: read | Source GPR. | ## Register Effects ### `lfs` - **Reads (always):** `RA0`, `d` - **Reads (conditional):** _none_ - **Writes (always):** `FD` - **Writes (conditional):** _none_ ### `lfsu` - **Reads (always):** `RA`, `d` - **Reads (conditional):** _none_ - **Writes (always):** `FD`, `RA` - **Writes (conditional):** _none_ ### `lfsux` - **Reads (always):** `RA`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `FD`, `RA` - **Writes (conditional):** _none_ ### `lfsx` - **Reads (always):** `RA0`, `RB` - **Reads (conditional):** _none_ - **Writes (always):** `FD` - **Writes (conditional):** _none_ ## Status-Register Effects _No condition-register or status-register effects._ ## Operation (pseudocode) ``` EA <- (RA|0) + EXTS(d) FRT <- DoubleFromSingle(MEM(EA, 4)) ``` ## C Translation Example ```c /* No hand-written C yet. Translate the Canary emitter snapshot */ /* under Implementation References; its HIR maps directly: */ /* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */ /* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */ /* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */ /* wrap them in f.ByteSwap for the big-endian guest value */ /* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */ /* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */ /* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */ /* The Register Effects and Status-Register Effects tables above */ /* enumerate every side effect a faithful translation must emit. */ ``` ## Implementation References **`lfs`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfs"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:960`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L960) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:117`](../../../crates/sylpheed-ppc/src/opcode.rs#L117) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:486`](../../../crates/sylpheed-ppc/src/decoder.rs#L486)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfs(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + EXTS(D) // FRT <- DOUBLE(MEM(EA, 4)) Value* ea = CalculateEA_0_i(f, i.D.RA, XEEXTS16(i.D.DS)); Value* rt = f.Convert( f.Cast(f.ByteSwap(f.Load(ea, INT32_TYPE)), FLOAT32_TYPE), FLOAT64_TYPE); f.StoreFPR(i.D.RT, rt); return 0; } ```
**`lfsu`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfsu"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:974`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L974) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:118`](../../../crates/sylpheed-ppc/src/opcode.rs#L118) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:487`](../../../crates/sylpheed-ppc/src/decoder.rs#L487)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfsu(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + EXTS(D) // FRT <- DOUBLE(MEM(EA, 4)) // RA <- EA Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS)); Value* rt = f.Convert( f.Cast(f.ByteSwap(f.Load(ea, INT32_TYPE)), FLOAT32_TYPE), FLOAT64_TYPE); f.StoreFPR(i.D.RT, rt); StoreEA(f, i.D.RA, ea); return 0; } ```
**`lfsux`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfsux"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:986`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L986) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:119`](../../../crates/sylpheed-ppc/src/opcode.rs#L119) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:938`](../../../crates/sylpheed-ppc/src/decoder.rs#L938)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfsux(PPCHIRBuilder& f, const InstrData& i) { // EA <- (RA) + (RB) // FRT <- DOUBLE(MEM(EA, 4)) // RA <- EA Value* ea = CalculateEA(f, i.X.RA, i.X.RB); Value* rt = f.Convert( f.Cast(f.ByteSwap(f.Load(ea, INT32_TYPE)), FLOAT32_TYPE), FLOAT64_TYPE); f.StoreFPR(i.X.RT, rt); StoreEA(f, i.X.RA, ea); return 0; } ```
**`lfsx`** - Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lfsx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml) - Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:998`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L998) - Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:120`](../../../crates/sylpheed-ppc/src/opcode.rs#L120) - Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:934`](../../../crates/sylpheed-ppc/src/decoder.rs#L934)
Canary emitter (frozen snapshot @ f21ebd49e9) ```cpp int InstrEmit_lfsx(PPCHIRBuilder& f, const InstrData& i) { // if RA = 0 then // b <- 0 // else // b <- (RA) // EA <- b + (RB) // FRT <- DOUBLE(MEM(EA, 4)) Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB); Value* rt = f.Convert( f.Cast(f.ByteSwap(f.Load(ea, INT32_TYPE)), FLOAT32_TYPE), FLOAT64_TYPE); f.StoreFPR(i.X.RT, rt); return 0; } ```
## Special Cases & Edge Conditions - **Single → double in-register.** Reads 4 bytes as IEEE binary32, then exactly converts to binary64 (every binary32 has a representation in binary64). The result occupies all 64 bits of the FPR; subsequent FP arithmetic operates in double regardless of the value's origin. - **No FPSCR side effects.** The single→double widening is exact, so `lfs` cannot raise inexact, overflow, underflow, or invalid. A signalling NaN passes through unchanged into the FPR — it will signal at the next FP arithmetic instruction. - **Subnormals.** A binary32 subnormal expands to a binary64 normal — `lfs` quietly normalises. There is no "FPSCR[NI] non-IEEE mode" subnormal-to-zero behaviour applied at this stage on Xenon (NI affects arithmetic, not loads). - **`RA0` semantics.** In `lfs` / `lfsx`, `RA = 0` selects literal zero. Update forms `lfsu` / `lfsux` are invalid with `RA = 0`. - **Alignment.** Xenon tolerates unaligned 4-byte loads; PowerISA permits implementations to raise alignment exceptions for FP loads on cache-inhibited storage. - **Big-endian read.** Bytes `EA..EA+3` form the binary32 pattern, sign bit at `EA[7]`. Canary byte-swaps the loaded word, reinterprets it as binary32 and widens it with `vcvtss2sd`, carrying a NaN's quiet/signalling bit across unchanged. - **MSR[FP] required.** Disabled FP unit raises Floating-Point Unavailable. - **Pair with [`stfs`](stfs.md).** Store-single performs the inverse double→single rounding (which **can** raise FPSCR exceptions because that direction may be inexact). ## Related Instructions - [`lfd`](lfd.md) — double-precision load (no format conversion). - [`stfs`](stfs.md), [`stfsu`](stfs.md), [`stfsx`](stfs.md), [`stfsux`](stfs.md) — corresponding stores; these can round. - [`stfiwx`](stfiwx.md) — store-FP-as-integer-word. - [`lwz`](lwz.md) — integer word load (same width, GPR target). ## IBM Reference - [AIX 7.3 — `lfs` (Load Floating-Point Single)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lfs-load-floating-point-single-instruction) - [AIX 7.3 — `lfsu` / `lfsx` / `lfsux`](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lfsu-load-floating-point-single-update-instruction)