# `lswx` — Load String Word Indexed

> **Category:** [Memory](../categories/memory.md) · **Form:** [X](../forms/X.md) · **Opcode:** `0x7c00042a`

<!-- GENERATED: BEGIN -->

## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `lswx` | `lswx` | — | Load String Word Indexed |

## Syntax

```asm
(no disassembly template)
```

## Encoding

### `lswx` — form `X`

- **Opcode word:** `0x7c00042a`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `533`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |

## Register Effects

### `lswx`

- **Reads (always):** _none_
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`lswx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="lswx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:732`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L732)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:134`](../../../crates/sylpheed-ppc/src/opcode.rs#L134)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:932`](../../../crates/sylpheed-ppc/src/decoder.rs#L932)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_lswx(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}
```
</details>

<!-- GENERATED: END -->

## Special Cases & Edge Conditions

- **Byte count from `XER[25..31]`.** Unlike `lswi` (where the count is encoded as `RB`), `lswx` reads `XER[25..31]` for the byte count `NB` (0..127). `NB = 0` is **not** the "32 bytes" special case here — zero means literally zero bytes, no registers touched. ⚠️ Canary does not implement `lswx`: its emitter is `XEINSTRNOTIMPLEMENTED`, so translating one logs "Unimplemented instr" and, with the default `break_on_unimplemented_instructions`, breaks.
- **Register packing identical to `lswi`.** Bytes are packed big-endian into successive GPRs starting at `RT`, four bytes per register, with wraparound `r31 → r0`. Trailing bytes in the last register are zero-padded on the right.
- **`RA0` semantics.** `RA = 0` selects literal zero. The instruction has no update form — `RA` is not modified.
- **Invalid forms.** AIX flags as invalid: `RT` collides with `RA` or `RB` within the destination range; `XER[25..31]` and `NB` byte stream wraps around through both `RA` and `RB`. Canary does not implement `lswx` (`XEINSTRNOTIMPLEMENTED`).
- **Used for non-multiple-of-4 copies.** Together with `lswi`, gives a way to load a runtime-determined byte count without per-byte loops. Compilers don't emit it; rare hand-written copy primitives may.
- **Alignment.** Architecture allows arbitrary alignment; cache-inhibited storage may raise alignment exceptions on real hardware.
- **No FPSCR / CR effects.** Pure data movement.

## Related Instructions

- [`lswi`](lswi.md) — sibling with byte count encoded as `RB` field (immediate-style).
- [`stswx`](stswx.md), [`stswi`](stswi.md) — symmetric stores.
- [`lmw`](lmw.md) — word-granular bulk load (no byte tail handling).
- [`lwz`](lwz.md), [`lbz`](lbz.md) — scalar loads compilers actually emit.

## IBM Reference

- [AIX 7.3 — `lswx` (Load String Word Indexed)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-lswx-load-string-word-indexed-instruction)
- `PowerISA v2.07B Book II` § "Load and Store String" for invalid-form rules and `XER` interaction.