# `vcmpequw` — Vector Compare Equal-to Unsigned Word
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x10000086`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vcmpequw` | `vcmpequw` | — | Vector Compare Equal-to Unsigned Word |
| `vcmpequw.` | `vcmpequw` | Rc=1 | Vector Compare Equal-to Unsigned Word |
| `vcmpequw128` | `vcmpequw128` | — | Vector128 Compare Equal-to Unsigned Word |
| `vcmpequw128.` | `vcmpequw128` | Rc=1 | Vector128 Compare Equal-to Unsigned Word |
## Syntax
```asm
vcmpequw[Rc] [VD], [VA], [VB]
vcmpequw128[Rc] [VD], [VA], [VB]
```
## Encoding
### `vcmpequw` — form `VC`
- **Opcode word:** `0x10000086`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `134`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21 | `Rc` | record-form flag (updates CR6) |
| 22–31 | `XO` | extended opcode (10 bits) |
### `vcmpequw128` — form `VX128_R`
- **Opcode word:** `0x18000200`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `512`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `VA128l` | source A low 5 bits |
| 16–20 | `VB128l` | source B low 5 bits |
| 21 | `VA128H` | source A high bit |
| 22–25 | `XO` | extended opcode (compare) |
| 26 | `VA128h` | source A middle bit |
| 27 | `Rc` | record-form flag (updates CR6) |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VA` | vcmpequw: read; vcmpequw128: read | Source A vector register. |
| `VB` | vcmpequw: read; vcmpequw128: read | Source B vector register. |
| `VD` | vcmpequw: write; vcmpequw128: write | Destination vector register. |
| `CR` | vcmpequw: write (conditional); vcmpequw128: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
## Register Effects
### `vcmpequw`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`
### `vcmpequw128`
- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`
## Status-Register Effects
- `vcmpequw`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
- `vcmpequw128`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vcmpequw`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpequw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:727`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L727)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:327`](../../../crates/sylpheed-ppc/src/opcode.rs#L327)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:674`](../../../crates/sylpheed-ppc/src/decoder.rs#L674)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_vcmpequw(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vcmpxxi_(f, i, vcmpxxi_eq, 4, i.VXR.VD, i.VXR.VA, i.VXR.VB,
i.VXR.Rc);
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_vcmpequw128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vcmpxxi_(f, i, vcmpxxi_eq, 4, VX128_R_VD128, VX128_R_VA128,
VX128_R_VB128, i.VX128_R.Rc);
}
```