# `vcmpgtuw` — Vector Compare Greater-Than Unsigned Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VC](../forms/VC.md) · **Opcode:** `0x10000286`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vcmpgtuw` | `vcmpgtuw` | — | Vector Compare Greater-Than Unsigned Word |
| `vcmpgtuw.` | `vcmpgtuw` | Rc=1 | Vector Compare Greater-Than Unsigned Word |

## Syntax

```asm
vcmpgtuw[Rc] [VD], [VA], [VB]
```

## Encoding

### `vcmpgtuw` — form `VC`

- **Opcode word:** `0x10000286`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `646`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21 | `Rc` | record-form flag (updates CR6) |
| 22–31 | `XO` | extended opcode (10 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vcmpgtuw: read | Source A vector register. |
| `VB` | vcmpgtuw: read | Source B vector register. |
| `VD` | vcmpgtuw: write | Destination vector register. |
| `CR` | vcmpgtuw: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |

## Register Effects

### `vcmpgtuw`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `vcmpgtuw`: **CR6** ← `[all-true, 0, all-false, 0]` when `Rc=1`.

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vcmpgtuw`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vcmpgtuw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:755`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L755)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:338`](../../../crates/sylpheed-ppc/src/opcode.rs#L338)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:679`](../../../crates/sylpheed-ppc/src/decoder.rs#L679)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vcmpgtuw(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vcmpxxi_(f, i, vcmpxxi_gt_unsigned, 4, i.VXR.VD, i.VXR.VA,
                            i.VXR.VB, i.VXR.Rc);
}
```
</details>

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## Special Cases & Edge Conditions

- **Per-word mask: all-ones / all-zero.** Four word lanes; `VD[i] = (uint32(VA[i]) > uint32(VB[i])) ? 0xFFFFFFFF : 0`. Lane 0 is the most-significant word.
- **Sign matters.** `0x8000_0000 > 0x0000_0001` is `true` unsigned but `false` signed.
- **CR6 update when `Rc=1`** (`vcmpgtuw.`). CR6 = `[lt = all-true, gt = 0, eq = all-false, so = 0]`.
- **Compose with `vsel`.** Mask drives [`vsel`](vsel.md) per word.
- **Common usage.** Hashtable bucket selection, packed-RGBA bit-pattern ordering, ID range checks.
- **No `VSCR` interaction, no XER, no traps.**
- **Aliasing legal.**
- **No VMX128 sibling.**

## Related Instructions

- [`vcmpgtsw`](vcmpgtsw.md) — same width, signed `>`.
- [`vcmpequw`](vcmpequw.md) — equality at word width.
- [`vcmpgtub`](vcmpgtub.md), [`vcmpgtuh`](vcmpgtuh.md) — unsigned `>` at byte / half width.
- [`vsel`](vsel.md), [`vand`](vand.md), [`vandc`](vandc.md), [`vor`](vor.md), [`vxor`](vxor.md) — mask consumers / combinators.
- [`vmaxuw`](vmaxuw.md), [`vminuw`](vminuw.md) — direct unsigned max / min.

## IBM Reference

- [AIX 7.3 — `vcmpgtuw` (Vector Compare Greater-Than Unsigned Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vcmpgtuw-vector-compare-greater-than-unsigned-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Vector Compares](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)