# `vmulosh` — Vector Multiply Odd Signed Half Word

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000148`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmulosh` | `vmulosh` | — | Vector Multiply Odd Signed Half Word |

## Syntax

```asm
vmulosh [VD], [VA], [VB]
```

## Encoding

### `vmulosh` — form `VX`

- **Opcode word:** `0x10000148`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `328`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmulosh: read | Source A vector register. |
| `VB` | vmulosh: read | Source B vector register. |
| `VD` | vmulosh: write | Destination vector register. |

## Register Effects

### `vmulosh`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmulosh`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmulosh"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1096`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1096)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:391`](../../../crates/sylpheed-ppc/src/opcode.rs#L391)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:577`](../../../crates/sylpheed-ppc/src/decoder.rs#L577)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vmulosh(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}
```
</details>

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## Special Cases & Edge Conditions

- **Odd-lane signed half-word multiply.** Only half-word lanes 1, 3, 5, 7 of `VA` and `VB` (big-endian numbering) participate. Each pair is treated as signed 16-bit, multiplied, and sign-extended to a signed 32-bit word in `VD`. Pairing: `VD.w[i] = (int16)VA.h[2*i+1] * (int16)VB.h[2*i+1]` for `i ∈ 0..3`.
- **Lane-count reduction.** 8 half-word lanes → 4 word lanes.
- **No overflow.** `(-32768)*(-32768) = 0x40000000` — fits in int32. `VSCR[SAT]` is untouched.
- **Pair with [`vmulesh`](vmulesh.md)** for all eight products, then interleave with `vmrghw`/`vmrglw`. Feed into [`vmsumshm`](vmsumshm.md)/[`vmsumshs`](vmsumshs.md) for accumulation.
- **Signed arithmetic.** Negative inputs sign-extend before multiplication; contrast with [`vmulouh`](vmulouh.md).
- **No `Rc`, no XER.** No VMX128 sibling.

## Related Instructions

- [`vmulesh`](vmulesh.md) — even-lane signed half-word multiply.
- [`vmulouh`](vmulouh.md), [`vmuleuh`](vmuleuh.md) — unsigned half-word twins.
- [`vmulosb`](vmulosb.md), [`vmulesb`](vmulesb.md) — signed byte even/odd.
- [`vmhaddshs`](vmhaddshs.md), [`vmhraddshs`](vmhraddshs.md) — fused half-word fixed-point MAC variants.
- [`vmsumshm`](vmsumshm.md), [`vmsumshs`](vmsumshs.md) — signed multiply-sum modulo / saturating.

## IBM Reference

- [AIX 7.3 — `vmulosh` (Vector Multiply Odd Signed Half Word)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmulosh-vector-multiply-odd-signed-half-word-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)