# `vsrab` — Vector Shift Right Algebraic Byte

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x10000304`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vsrab` | `vsrab` | — | Vector Shift Right Algebraic Byte |

## Syntax

```asm
vsrab [VD], [VA], [VB]
```

## Encoding

### `vsrab` — form `VX`

- **Opcode word:** `0x10000304`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `772`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vsrab: read | Source A vector register. |
| `VB` | vsrab: read | Source B vector register. |
| `VD` | vsrab: write | Destination vector register. |

## Register Effects

### `vsrab`

- **Reads (always):** `VA`, `VB`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vsrab`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vsrab"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1585`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1585)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:458`](../../../crates/sylpheed-ppc/src/opcode.rs#L458)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:615`](../../../crates/sylpheed-ppc/src/decoder.rs#L615)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vsrab(PPCHIRBuilder& f, const InstrData& i) {
  // (VD) <- (VA) >>a (VB) by bytes
  Value* v = f.VectorSha(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT8_TYPE);
  f.StoreVR(i.VX.VD, v);
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Per-lane arithmetic right-shift of signed bytes.** `VD.b[i] = (int8)VA.b[i] >> (VB.b[i] & 7)` — sign bit propagates into vacated high-order bits. Low 3 bits of each shift-count byte are honoured.
- **Per-lane shift counts.** Splat via [`vspltb`](vspltb.md) / [`vspltisb`](vspltisb.md) for uniform shifts.
- **Sign extension.** Negative inputs produce values that stay negative (toward `-1`), unlike logical shift [`vsrb`](vsrb.md) which zero-fills.
- **Big-endian byte lanes.**
- **No flags, no VSCR.**
- **No VMX128 sibling.**

## Related Instructions

- [`vsrb`](vsrb.md) — logical-right byte shift.
- [`vslb`](vslb.md) — byte logical-left.
- [`vrlb`](vrlb.md) — byte rotate.
- [`vsrah`](vsrah.md), [`vsraw`](vsraw.md) — arithmetic-right half-word / word.

## IBM Reference

- [AIX 7.3 — `vsrab` (Vector Shift Right Arithmetic Integer Byte)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vsrab-vector-shift-right-algebraic-integer-byte-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Shift / Rotate](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)