# `fdivx` — Floating Divide

> **Category:** [Floating-Point](../categories/fpu.md) · **Form:** [A](../forms/A.md) · **Opcode:** `0xfc000024`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `fdiv` | `fdivx` | — | Floating Divide |
| `fdiv.` | `fdivx` | Rc=1 | Floating Divide |

## Syntax

```asm
fdiv[Rc] [FD], [FA], [FB]
```

## Encoding

### `fdivx` — form `A`

- **Opcode word:** `0xfc000024`
- **Primary opcode (bits 0–5):** `63`
- **Extended opcode:** `18`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (59 or 63) |
| 6–10 | `FRT` | destination FPR |
| 11–15 | `FRA` | source A FPR |
| 16–20 | `FRB` | source B FPR |
| 21–25 | `FRC` | source C FPR (multiplier for madd-style ops) |
| 26–30 | `XO` | extended opcode (5 bits) |
| 31 | `Rc` | record-form flag (updates CR1) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `FA` | fdivx: read | Source A floating-point register (`fr0`–`fr31`). |
| `FB` | fdivx: read | Source B floating-point register. |
| `FD` | fdivx: write | Destination floating-point register. |
| `CR` | fdivx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `FPSCR` | fdivx: write | Floating-Point Status and Control Register. |

## Register Effects

### `fdivx`

- **Reads (always):** `FA`, `FB`
- **Reads (conditional):** _none_
- **Writes (always):** `FD`, `FPSCR`
- **Writes (conditional):** `CR`

## Status-Register Effects

- `fdivx`: **CR1** ← FPSCR[FX, FEX, VX, OX] when `Rc=1`.; **FPSCR** updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

## Operation (pseudocode)

```
FRT <- FRA ÷ FRB
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`fdivx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="fdivx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_fpu.cc:55`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_fpu.cc#L55)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:75`](../../../crates/sylpheed-ppc/src/opcode.rs#L75)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:1035`](../../../crates/sylpheed-ppc/src/decoder.rs#L1035)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_fdivx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- frA / frB
#if XE_PLATFORM_LINUX
  // TODO(has207): verify if this is needed on Windows
  // On Linux, fdiv needs to use A format fields instead of X format
  Value* v = f.Div(f.LoadFPR(i.A.FRA), f.LoadFPR(i.A.FRB));
  f.StoreFPR(i.A.FRT, v);
  f.UpdateFPSCR(v, i.A.Rc);
#else
  Value* v = f.Div(f.LoadFPR(i.X.RA), f.LoadFPR(i.X.RB));
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
#endif
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Double precision.** Operates on IEEE-754 binary64; [`fdivsx`](fdivsx.md) is the single-precision sibling.
- **Divide by zero.** `FRA / ±0` (with `FRA` finite, non-zero) sets `FPSCR[ZX, FX]` and produces a correctly-signed infinity. Canary's `vdivsd` produces the same ±∞ — but does not raise `ZX` (`UpdateFPSCR` is a stub). **Canary quirk:** title code that polls FPSCR for divide-by-zero will not observe it.
- **`0 / 0`** sets `FPSCR[VXZDZ, VX, FX]` and yields a quiet NaN.
- **`±∞ / ±∞`** sets `FPSCR[VXIDI, VX, FX]` and yields a quiet NaN.
- **FPSCR side effects.** Hardware updates `FPRF`, `FR`, `FI`, `FX` plus exception bits `OX`, `UX`, `XX`, `ZX`, `VXZDZ`, `VXIDI`, `VXSNAN`. Canary does not maintain these: its `UpdateFPSCR` is a stub that clears `FEX`/`VX` and, with `Rc=1`, writes CR1 as all zeros.
- **`Rc=1` (`fdiv.`)** copies `FPSCR[FX, FEX, VX, OX]` into CR1.
- **NaN propagation.** Quiet-NaN result for any NaN operand; signalling NaNs are quietened.
- **Performance.** Hardware divide is multi-cycle and not pipelined on Xenon. Many titles prefer `fres`/`frsqrte` followed by Newton-Raphson refinement (or by `fmadd` chains) to avoid the divider.
- **Denormal flush.** That Xenon boots with `FPSCR[NI]=1` is unverified. Canary starts every guest thread in IEEE mode (MXCSR `0x1F80`; its init comment flags the startup state as unchecked) and turns on the host's flush-to-zero (`MXCSR.FZ`) only when the guest sets `NI` through `mtfsf`/`mtfsfi`.
- **Encoding.** A-form, primary 63, XO 18. `FRC` is don't-care.

## Related Instructions

- [`fdivsx`](fdivsx.md) — single-precision divide.
- [`fresx`](fresx.md) — reciprocal estimate `~1/FRB`; combined with `fmul`/`fmadd` to implement reciprocal divides.
- [`fmulx`](fmulx.md), [`faddx`](faddx.md), [`fsubx`](fsubx.md) — companion arithmetic.
- [`fmaddx`](fmaddx.md), [`fnmsubx`](fnmsubx.md) — used in Newton-Raphson refinement steps.
- [`mffsx`](../control/mffsx.md), [`mtfsfx`](../control/mtfsfx.md) — FPSCR control (rounding mode, exception masks).

## IBM Reference

- [AIX 7.3 — `fdiv` (Floating Divide)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-fd-fdiv-floating-divide-instruction)
- [PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor](https://openpowerfoundation.org/specifications/isa/) (divide-by-zero and invalid-operation rules).