# `vspltw` — Vector Splat Word
> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VX](../forms/VX.md) · **Opcode:** `0x1000028c`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vspltw` | `vspltw` | — | Vector Splat Word |
| `vspltw128` | `vspltw128` | — | Vector128 Splat Word |
## Syntax
```asm
vspltw [VD], [VB], [UIMM]
vspltw128 [VD], [VB], [UIMM]
```
## Encoding
### `vspltw` — form `VX`
- **Opcode word:** `0x1000028c`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `652`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT/VD` | destination vector register |
| 11–15 | `VRA/VA` | source A vector register |
| 16–20 | `VRB/VB` | source B vector register |
| 21–31 | `XO` | extended opcode (11 bits) |
### `vspltw128` — form `VX128_3`
- **Opcode word:** `0x18000730`
- **Primary opcode (bits 0–5):** `6`
- **Extended opcode:** `1840`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (6) |
| 6–10 | `VD128l` | destination low 5 bits |
| 11–15 | `IMM` | 5-bit immediate |
| 16–20 | `VB128l` | source B low 5 bits |
| 21–27 | `XO` | extended opcode |
| 28–29 | `VD128h` | destination high 2 bits |
| 30–31 | `VB128h` | source B high 2 bits |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `VB` | vspltw: read; vspltw128: read | Source B vector register. |
| `UIMM` | vspltw: read; vspltw128: read | 16-bit unsigned immediate. Zero-extended. |
| `VD` | vspltw: write; vspltw128: write | Destination vector register. |
## Register Effects
### `vspltw`
- **Reads (always):** `VB`, `UIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
### `vspltw128`
- **Reads (always):** `VB`, `UIMM`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```
## C Translation Example
```c
/* No hand-written C yet. Translate the Canary emitter snapshot */
/* under Implementation References; its HIR maps directly: */
/* f.LoadGPR(n) / f.StoreGPR(n, v) -> r[n] / r[n] = v */
/* f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n] */
/* f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters */
/* wrap them in f.ByteSwap for the big-endian guest value */
/* f.UpdateCR(n, v) -> CR field n from v's LOW 32 BITS vs 0 */
/* f.LoadCA / f.StoreCA -> xer.CA; f.StoreSAT -> vscr.SAT */
/* i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands */
/* The Register Effects and Status-Register Effects tables above */
/* enumerate every side effect a faithful translation must emit. */
```
## Implementation References
**`vspltw`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vspltw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1515`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1515)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:455`](../../../crates/sylpheed-ppc/src/opcode.rs#L455)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:608`](../../../crates/sylpheed-ppc/src/decoder.rs#L608)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_vspltw(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vspltw_(f, i.VX.VD, i.VX.VB, i.VX.VA);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1507) ──
int InstrEmit_vspltw_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
uint32_t uimm) {
// (VD.xyzw) <- (VB.uimm)
Value* w = f.Extract(f.LoadVR(vb), uimm & 0x3, INT32_TYPE);
Value* v = f.Splat(w, VEC128_TYPE);
f.StoreVR(vd, v);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_vspltw128(PPCHIRBuilder& f, const InstrData& i) {
return InstrEmit_vspltw_(f, VX128_3_VD128, VX128_3_VB128, VX128_3_IMM);
}
// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:1507) ──
int InstrEmit_vspltw_(PPCHIRBuilder& f, uint32_t vd, uint32_t vb,
uint32_t uimm) {
// (VD.xyzw) <- (VB.uimm)
Value* w = f.Extract(f.LoadVR(vb), uimm & 0x3, INT32_TYPE);
Value* v = f.Splat(w, VEC128_TYPE);
f.StoreVR(vd, v);
return 0;
}
```