{
  "description": "PowerPC instructions implemented in Xenia Canary (Xbox 360 emulator)",
  "source": "tools/ppc-instructions.xml",
  "generator": "Generated from ppc-instructions.xml via tools/ppc-table-gen.py",
  "statistics": {
    "total_instructions": 455,
    "encoding_formats": 27,
    "by_category": {
      "Integer / ALU": {
        "total": 70,
        "vmx128": 0,
        "standard": 70
      },
      "Branch / System": {
        "total": 9,
        "vmx128": 0,
        "standard": 9
      },
      "Condition Register / SPR": {
        "total": 26,
        "vmx128": 0,
        "standard": 26
      },
      "Floating-Point": {
        "total": 33,
        "vmx128": 0,
        "standard": 33
      },
      "Memory (Load/Store/Cache)": {
        "total": 112,
        "vmx128": 15,
        "standard": 97
      },
      "Vector / VMX (AltiVec)": {
        "total": 205,
        "vmx128": 61,
        "standard": 144
      }
    },
    "by_encoding_format": {
      "A": 21,
      "B": 1,
      "D": 40,
      "DCBZ": 2,
      "DS": 5,
      "I": 1,
      "M": 3,
      "MD": 4,
      "MDS": 2,
      "SC": 1,
      "VA": 14,
      "VC": 13,
      "VX": 117,
      "VX128": 34,
      "VX128_1": 16,
      "VX128_2": 1,
      "VX128_3": 15,
      "VX128_4": 2,
      "VX128_5": 1,
      "VX128_P": 1,
      "VX128_R": 5,
      "X": 117,
      "XFL": 1,
      "XFX": 4,
      "XL": 12,
      "XO": 21,
      "XS": 1
    }
  },
  "source_files": {
    "definition": "tools/ppc-instructions.xml",
    "code_generator": "tools/ppc-table-gen.py",
    "generated": {
      "opcode_enum": "src/xenia/cpu/ppc/ppc_opcode.h",
      "opcode_table": "src/xenia/cpu/ppc/ppc_opcode_table_gen.cc",
      "opcode_lookup": "src/xenia/cpu/ppc/ppc_opcode_lookup_gen.cc",
      "disassembler": "src/xenia/cpu/ppc/ppc_opcode_disasm_gen.cc"
    },
    "emit_handlers": {
      "alu": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "control": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "memory": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "fpu": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "altivec": "src/xenia/cpu/ppc/ppc_emit_altivec.cc"
    },
    "backends": {
      "x64": "src/xenia/cpu/backend/x64/",
      "a64": "src/xenia/cpu/backend/a64/"
    }
  },
  "instructions": [
    {
      "mnemonic": "addx",
      "description": "Add",
      "opcode": "7c000214",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "add[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "addcx",
      "description": "Add Carrying",
      "opcode": "7c000014",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "addc[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "addex",
      "description": "Add Extended",
      "opcode": "7c000114",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "adde[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "addi",
      "description": "Add Immediate",
      "opcode": "38000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "addi [RD], [RA0], [SIMM]"
    },
    {
      "mnemonic": "addic",
      "description": "Add Immediate Carrying",
      "opcode": "30000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "addic [RD], [RA], [SIMM]"
    },
    {
      "mnemonic": "addic.",
      "description": "Add Immediate Carrying and Record",
      "opcode": "34000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "disassembly": "addic. [RD], [RA], [SIMM]"
    },
    {
      "mnemonic": "addis",
      "description": "Add Immediate Shifted",
      "opcode": "3c000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "addis [RD], [RA0], [SIMM]"
    },
    {
      "mnemonic": "addmex",
      "description": "Add to Minus One Extended",
      "opcode": "7c0001d4",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "addme[OE][Rc] [RD], [RA]"
    },
    {
      "mnemonic": "addzex",
      "description": "Add to Zero Extended",
      "opcode": "7c000194",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "addze[OE][Rc] [RD], [RA]"
    },
    {
      "mnemonic": "andx",
      "description": "AND",
      "opcode": "7c000038",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "and[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "andcx",
      "description": "AND with Complement",
      "opcode": "7c000078",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "andc[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "andi.",
      "description": "AND Immediate",
      "opcode": "70000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "disassembly": "andi. [RA], [RS], [UIMM]"
    },
    {
      "mnemonic": "andis.",
      "description": "AND Immediate Shifted",
      "opcode": "74000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "disassembly": "andis. [RA], [RS], [UIMM]"
    },
    {
      "mnemonic": "bx",
      "description": "Branch",
      "opcode": "48000000",
      "form": "I",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "LK",
          "conditional": false
        },
        {
          "field": "AA",
          "conditional": false
        },
        {
          "field": "ADDR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "LR",
          "conditional": true
        }
      ],
      "disassembly": "b[LK][AA] [ADDR]"
    },
    {
      "mnemonic": "bcx",
      "description": "Branch Conditional",
      "opcode": "40000000",
      "form": "B",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "LK",
          "conditional": false
        },
        {
          "field": "AA",
          "conditional": false
        },
        {
          "field": "BO",
          "conditional": false
        },
        {
          "field": "BI",
          "conditional": false
        },
        {
          "field": "ADDR",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "CTR",
          "conditional": true
        }
      ],
      "outputs": [
        {
          "field": "CTR",
          "conditional": true
        },
        {
          "field": "LR",
          "conditional": true
        }
      ],
      "disassembly": "bc[LK][AA] [BO], [BI], [ADDR]"
    },
    {
      "mnemonic": "bcctrx",
      "description": "Branch Conditional to Count Register",
      "opcode": "4c000420",
      "form": "XL",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "LK",
          "conditional": false
        },
        {
          "field": "BO",
          "conditional": false
        },
        {
          "field": "BI",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": false
        },
        {
          "field": "CTR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "LR",
          "conditional": true
        }
      ],
      "disassembly": "bcctr[LK] [BO], [BI]"
    },
    {
      "mnemonic": "bclrx",
      "description": "Branch Conditional to Link Register",
      "opcode": "4c000020",
      "form": "XL",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "LK",
          "conditional": false
        },
        {
          "field": "BO",
          "conditional": false
        },
        {
          "field": "BI",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "CTR",
          "conditional": true
        }
      ],
      "outputs": [
        {
          "field": "CTR",
          "conditional": true
        },
        {
          "field": "LR",
          "conditional": true
        }
      ],
      "disassembly": "bclr[LK] [BO], [BI]"
    },
    {
      "mnemonic": "cmp",
      "description": "Compare",
      "opcode": "7c000000",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "L",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        }
      ],
      "disassembly": "cmp [CRFD], [L], [RA], [RB]"
    },
    {
      "mnemonic": "cmpi",
      "description": "Compare Immediate",
      "opcode": "2c000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "L",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CRFD",
          "conditional": false
        }
      ],
      "disassembly": "cmpi [CRFD], [L], [RA], [SIMM]"
    },
    {
      "mnemonic": "cmpl",
      "description": "Compare Logical",
      "opcode": "7c000040",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "L",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        }
      ],
      "disassembly": "cmpl [CRFD], [L], [RA], [RB]"
    },
    {
      "mnemonic": "cmpli",
      "description": "Compare Logical Immediate",
      "opcode": "28000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "L",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        }
      ],
      "disassembly": "cmpli [CRFD], [L], [RA], [UIMM]"
    },
    {
      "mnemonic": "cntlzdx",
      "description": "Count Leading Zeros Doubleword",
      "opcode": "7c000074",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "cntlzd [RA], [RS]"
    },
    {
      "mnemonic": "cntlzwx",
      "description": "Count Leading Zeros Word",
      "opcode": "7c000034",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "cntlzw[Rc] [RA], [RS]"
    },
    {
      "mnemonic": "crand",
      "description": "Condition Register AND",
      "opcode": "4c000202",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "crand [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "crandc",
      "description": "Condition Register AND with Complement",
      "opcode": "4c000102",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "crandc [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "creqv",
      "description": "Condition Register Equivalent",
      "opcode": "4c000242",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "creqv [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "crnand",
      "description": "Condition Register NAND",
      "opcode": "4c0001c2",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "crnand [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "crnor",
      "description": "Condition Register NOR",
      "opcode": "4c000042",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "crnor [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "cror",
      "description": "Condition Register OR",
      "opcode": "4c000382",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "cror [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "crorc",
      "description": "Condition Register OR with Complement",
      "opcode": "4c000342",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "crorc [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "crxor",
      "description": "Condition Register XOR",
      "opcode": "4c000182",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRBA",
          "conditional": false
        },
        {
          "field": "CRBB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRBD",
          "conditional": false
        }
      ],
      "disassembly": "crxor [CRBD], [CRBA], [CRBB]"
    },
    {
      "mnemonic": "dcbf",
      "description": "Data Cache Block Flush",
      "opcode": "7c0000ac",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbf [RA0], [RB]"
    },
    {
      "mnemonic": "dcbi",
      "description": "Data Cache Block Invalidate",
      "opcode": "7c0003ac",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbi [RA0], [RB]"
    },
    {
      "mnemonic": "dcbst",
      "description": "Data Cache Block Store",
      "opcode": "7c00006c",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbst [RA0], [RB]"
    },
    {
      "mnemonic": "dcbt",
      "description": "Data Cache Block Touch",
      "opcode": "7c00022c",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbt [RA0], [RB]"
    },
    {
      "mnemonic": "dcbtst",
      "description": "Data Cache Block Touch for Store",
      "opcode": "7c0001ec",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbtst [RA0], [RB]"
    },
    {
      "mnemonic": "dcbz",
      "description": "Data Cache Block Clear to Zero",
      "opcode": "7c0007ec",
      "form": "DCBZ",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbz [RA0], [RB]"
    },
    {
      "mnemonic": "dcbz128",
      "description": "Data Cache Block Clear to Zero 128",
      "opcode": "7c2007ec",
      "form": "DCBZ",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "dcbz128 [RA0], [RB]"
    },
    {
      "mnemonic": "divdx",
      "description": "Divide Doubleword",
      "opcode": "7c0003d2",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "divd[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "divdux",
      "description": "Divide Doubleword Unsigned",
      "opcode": "7c000392",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "divdu[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "divwx",
      "description": "Divide Word",
      "opcode": "7c0003d6",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "divw[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "divwux",
      "description": "Divide Word Unsigned",
      "opcode": "7c000396",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "divwu[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "eieio",
      "description": "Enforce In-Order Execution of I/O",
      "opcode": "7c0006ac",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": "eieio"
    },
    {
      "mnemonic": "eqvx",
      "description": "Equivalent",
      "opcode": "7c000238",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "eqv[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "extsbx",
      "description": "Extend Sign Byte",
      "opcode": "7c000774",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "extsb[Rc] [RA], [RS]"
    },
    {
      "mnemonic": "extshx",
      "description": "Extend Sign Half Word",
      "opcode": "7c000734",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "extsh[Rc] [RA], [RS]"
    },
    {
      "mnemonic": "extswx",
      "description": "Extend Sign Word",
      "opcode": "7c0007B4",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "extsw[Rc] [RA], [RS]"
    },
    {
      "mnemonic": "fabsx",
      "description": "Floating Absolute Value",
      "opcode": "fc000210",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "fabs[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "faddx",
      "description": "Floating Add",
      "opcode": "fc00002a",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fadd[Rc] [FD], [FA], [FB]"
    },
    {
      "mnemonic": "faddsx",
      "description": "Floating Add Single",
      "opcode": "ec00002a",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fadds[Rc] [FD], [FA], [FB]"
    },
    {
      "mnemonic": "fcfidx",
      "description": "Floating Convert From Integer Doubleword",
      "opcode": "FC00069C",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fcfid[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fcmpo",
      "description": "Floating Compare Ordered",
      "opcode": "fc000040",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fcmpo [CRFD], [FA], [FB]"
    },
    {
      "mnemonic": "fcmpu",
      "description": "Floating Compare Unordered",
      "opcode": "fc000000",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fcmpu [CRFD], [FA], [FB]"
    },
    {
      "mnemonic": "fctidx",
      "description": "Floating Convert to Integer Doubleword",
      "opcode": "fc00065c",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fctid[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fctidzx",
      "description": "Floating Convert to Integer Doubleword with Round Toward Zero",
      "opcode": "fc00065e",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fctidz[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fctiwx",
      "description": "Floating Convert to Integer Word",
      "opcode": "fc00001c",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fctiw[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fctiwzx",
      "description": "Floating Convert to Integer Word with Round Toward Zero",
      "opcode": "fc00001e",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fctiwz[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fdivx",
      "description": "Floating Divide",
      "opcode": "fc000024",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fdiv[Rc] [FD], [FA], [FB]"
    },
    {
      "mnemonic": "fdivsx",
      "description": "Floating Divide Single",
      "opcode": "ec000024",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fdivs[Rc] [FD], [FA], [FB]"
    },
    {
      "mnemonic": "fmaddx",
      "description": "Floating Multiply-Add",
      "opcode": "fc00003a",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fmadd[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fmaddsx",
      "description": "Floating Multiply-Add Single",
      "opcode": "ec00003a",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fmadds[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fmrx",
      "description": "Floating Move Register",
      "opcode": "fc000090",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "fmr[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fmsubx",
      "description": "Floating Multiply-Subtract",
      "opcode": "fc000038",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fmsub[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fmsubsx",
      "description": "Floating Multiply-Subtract Single",
      "opcode": "ec000038",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fmsubs[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fmulx",
      "description": "Floating Multiply",
      "opcode": "fc000032",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fmul[Rc] [FD], [FA], [FC]"
    },
    {
      "mnemonic": "fmulsx",
      "description": "Floating Multiply Single",
      "opcode": "ec000032",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fmuls[Rc] [FD], [FA], [FC]"
    },
    {
      "mnemonic": "fnabsx",
      "description": "Floating Negative Absolute Value",
      "opcode": "fc000110",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "fnabs[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fnegx",
      "description": "Floating Negate",
      "opcode": "fc000050",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "fneg[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fnmaddx",
      "description": "Floating Negative Multiply-Add",
      "opcode": "fc00003e",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fnmadd[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fnmaddsx",
      "description": "Floating Negative Multiply-Add Single",
      "opcode": "ec00003e",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fnmadds[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fnmsubx",
      "description": "Floating Negative Multiply-Subtract",
      "opcode": "fc00003c",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fnmsub[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fnmsubsx",
      "description": "Floating Negative Multiply-Subtract Single",
      "opcode": "ec00003c",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fnmsubs[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fresx",
      "description": "Floating Reciprocal Estimate Single",
      "opcode": "ec000030",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fres[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "frspx",
      "description": "Floating Round to Single",
      "opcode": "fc000018",
      "form": "X",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "frsp[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "frsqrtex",
      "description": "Floating Reciprocal Square Root Estimate",
      "opcode": "fc000034",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "frsqrte[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fselx",
      "description": "Floating Select",
      "opcode": "fc00002e",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FC",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "fsel[Rc] [FD], [FA], [FC], [FB]"
    },
    {
      "mnemonic": "fsqrtx",
      "description": "Floating Square Root",
      "opcode": "fc00002c",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fsqrt[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fsqrtsx",
      "description": "Floating Square Root Single",
      "opcode": "ec00002c",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fsqrts[Rc] [FD], [FB]"
    },
    {
      "mnemonic": "fsubx",
      "description": "Floating Subtract",
      "opcode": "fc000028",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fsub[Rc] [FD], [FA], [FB]"
    },
    {
      "mnemonic": "fsubsx",
      "description": "Floating Subtract Single",
      "opcode": "ec000028",
      "form": "A",
      "group": "f",
      "category": "Floating-Point",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_fpu.cc",
      "inputs": [
        {
          "field": "FA",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "fsubs[Rc] [FD], [FA], [FB]"
    },
    {
      "mnemonic": "icbi",
      "description": "Instruction Cache Block Invalidate",
      "opcode": "7c0007ac",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "icbi [RA], [RB]"
    },
    {
      "mnemonic": "isync",
      "description": "Instruction Synchronize",
      "opcode": "4c00012c",
      "form": "XL",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": "isync"
    },
    {
      "mnemonic": "lbz",
      "description": "Load Byte and Zero",
      "opcode": "88000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lbz [RD], [d]([RA0])"
    },
    {
      "mnemonic": "lbzu",
      "description": "Load Byte and Zero with Update",
      "opcode": "8c000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lbzu [RD], [d]([RA])"
    },
    {
      "mnemonic": "lbzux",
      "description": "Load Byte and Zero with Update Indexed",
      "opcode": "7c0000ee",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lbzux [RD], [RA], [RB]"
    },
    {
      "mnemonic": "lbzx",
      "description": "Load Byte and Zero Indexed",
      "opcode": "7c0000ae",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lbzx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "ld",
      "description": "Load Doubleword",
      "opcode": "E8000000",
      "form": "DS",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "ds",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "ld [RD], [ds]([RA0])"
    },
    {
      "mnemonic": "ldarx",
      "description": "Load Doubleword and Reserve Indexed",
      "opcode": "7C0000A8",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "ldarx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "ldbrx",
      "description": "Load Doubleword Byte-Reverse Indexed",
      "opcode": "7C000428",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "ldbrx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "ldu",
      "description": "Load Doubleword with Update",
      "opcode": "E8000001",
      "form": "DS",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "ds",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "ldu [RD], [ds]([RA])"
    },
    {
      "mnemonic": "ldux",
      "description": "Load Doubleword with Update Indexed",
      "opcode": "7c00006a",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "ldux [RD], [RA], [RB]"
    },
    {
      "mnemonic": "ldx",
      "description": "Load Doubleword Indexed",
      "opcode": "7c00002a",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "ldx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lfd",
      "description": "Load Floating-Point Double",
      "opcode": "c8000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        }
      ],
      "disassembly": "lfd [FD], [d]([RA0])"
    },
    {
      "mnemonic": "lfdu",
      "description": "Load Floating-Point Double with Update",
      "opcode": "cc000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lfdu [FD], [d]([RA])"
    },
    {
      "mnemonic": "lfdux",
      "description": "Load Floating-Point Double with Update Indexed",
      "opcode": "7c0004ee",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lfdux [FD], [RA], [RB]"
    },
    {
      "mnemonic": "lfdx",
      "description": "Load Floating-Point Double Indexed",
      "opcode": "7c0004ae",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        }
      ],
      "disassembly": "lfdx [FD], [RA0], [RB]"
    },
    {
      "mnemonic": "lfs",
      "description": "Load Floating-Point Single",
      "opcode": "c0000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        }
      ],
      "disassembly": "lfs [FD], [d]([RA0])"
    },
    {
      "mnemonic": "lfsu",
      "description": "Load Floating-Point Single with Update",
      "opcode": "c4000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lfsu [FD], [d]([RA])"
    },
    {
      "mnemonic": "lfsux",
      "description": "Load Floating-Point Single with Update Indexed",
      "opcode": "7c00046e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lfsux [FD], [RA], [RB]"
    },
    {
      "mnemonic": "lfsx",
      "description": "Load Floating-Point Single Indexed",
      "opcode": "7c00042e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        }
      ],
      "disassembly": "lfsx [FD], [RA0], [RB]"
    },
    {
      "mnemonic": "lha",
      "description": "Load Half Word Algebraic",
      "opcode": "a8000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lha [RD], [d]([RA0])"
    },
    {
      "mnemonic": "lhau",
      "description": "Load Half Word Algebraic with Update",
      "opcode": "ac000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lhau [RD], [d]([RA])"
    },
    {
      "mnemonic": "lhaux",
      "description": "Load Half Word Algebraic with Update Indexed",
      "opcode": "7c0002ee",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lhaux [RD], [RA], [RB]"
    },
    {
      "mnemonic": "lhax",
      "description": "Load Half Word Algebraic Indexed",
      "opcode": "7c0002ae",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lhax [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lhbrx",
      "description": "Load Half Word Byte-Reverse Indexed",
      "opcode": "7c00062c",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lhbrx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lhz",
      "description": "Load Half Word and Zero",
      "opcode": "a0000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lhz [RD], [d]([RA0])"
    },
    {
      "mnemonic": "lhzu",
      "description": "Load Half Word and Zero with Update",
      "opcode": "a4000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lhzu [RD], [d]([RA])"
    },
    {
      "mnemonic": "lhzux",
      "description": "Load Half Word and Zero with Update Indexed",
      "opcode": "7c00026e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lhzux [RD], [RA], [RB]"
    },
    {
      "mnemonic": "lhzx",
      "description": "Load Half Word and Zero Indexed",
      "opcode": "7c00022e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lhzx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lmw",
      "description": "Load Multiple Word",
      "opcode": "b8000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": ""
    },
    {
      "mnemonic": "lswi",
      "description": "Load String Word Immediate",
      "opcode": "7c0004aa",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": ""
    },
    {
      "mnemonic": "lswx",
      "description": "Load String Word Indexed",
      "opcode": "7c00042a",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": ""
    },
    {
      "mnemonic": "lwa",
      "description": "Load Word Algebraic",
      "opcode": "e8000002",
      "form": "DS",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "ds",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lwa [RD], [ds]([RA0])"
    },
    {
      "mnemonic": "lwarx",
      "description": "Load Word and Reserve Indexed",
      "opcode": "7c000028",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lwarx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lwaux",
      "description": "Load Word Algebraic with Update Indexed",
      "opcode": "7c0002ea",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lwaux [RD], [RA], [RB]"
    },
    {
      "mnemonic": "lwax",
      "description": "Load Word Algebraic Indexed",
      "opcode": "7c0002aa",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lwax [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lwbrx",
      "description": "Load Word Byte-Reverse Indexed",
      "opcode": "7c00042c",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lwbrx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "lwz",
      "description": "Load Word and Zero",
      "opcode": "80000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lwz [RD], [d]([RA0])"
    },
    {
      "mnemonic": "lwzu",
      "description": "Load Word and Zero with Update",
      "opcode": "84000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lwzu [RD], [d]([RA])"
    },
    {
      "mnemonic": "lwzux",
      "description": "Load Word and Zero with Update Indexed",
      "opcode": "7c00006e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "lwzux [RD], [RA], [RB]"
    },
    {
      "mnemonic": "lwzx",
      "description": "Load Word and Zero Indexed",
      "opcode": "7c00002e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "lwzx [RD], [RA0], [RB]"
    },
    {
      "mnemonic": "mcrf",
      "description": "Move Condition Register Field",
      "opcode": "4c000000",
      "form": "XL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRFS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        }
      ],
      "disassembly": "mcrf [CRFD], [CRFS]"
    },
    {
      "mnemonic": "mcrfs",
      "description": "Move to Condition Register from FPSCR",
      "opcode": "fc000080",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CRFS",
          "conditional": false
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        },
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "disassembly": "mcrfs [CRFD], [CRFS]"
    },
    {
      "mnemonic": "mcrxr",
      "description": "Move to Condition Register from XER",
      "opcode": "7c000400",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        }
      ],
      "disassembly": "mcrxr [CRFD]"
    },
    {
      "mnemonic": "mfcr",
      "description": "Move from Condition Register",
      "opcode": "7c000026",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "mfcr [RD]"
    },
    {
      "mnemonic": "mffsx",
      "description": "Move from FPSCR",
      "opcode": "fc00048e",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "FPSCR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mffs[Rc] [RD]"
    },
    {
      "mnemonic": "mfmsr",
      "description": "Move from Machine State Register",
      "opcode": "7c0000a6",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "MSR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "mfmsr [RD]"
    },
    {
      "mnemonic": "mfspr",
      "description": "Move from Special-Purpose Register",
      "opcode": "7c0002a6",
      "form": "XFX",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "SPR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "mfspr [RD], [SPR]"
    },
    {
      "mnemonic": "mftb",
      "description": "Move from Time Base",
      "opcode": "7c0002e6",
      "form": "XFX",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "TBR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "mftb [RD], [TBR]"
    },
    {
      "mnemonic": "mtcrf",
      "description": "Move to Condition Register Fields",
      "opcode": "7c000120",
      "form": "XFX",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRM",
          "conditional": false
        }
      ],
      "disassembly": "mtcrf [CRM], [RS]"
    },
    {
      "mnemonic": "mtfsb0x",
      "description": "Move to FPSCR Bit 0",
      "opcode": "fc00008c",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [],
      "outputs": [
        {
          "field": "FPSCRD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mtfsb0[Rc] [FPSCRD]"
    },
    {
      "mnemonic": "mtfsb1x",
      "description": "Move to FPSCR Bit 1",
      "opcode": "fc00004c",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [],
      "outputs": [
        {
          "field": "FPSCRD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mtfsb1[Rc] [FPSCRD]"
    },
    {
      "mnemonic": "mtfsfx",
      "description": "Move to FPSCR Fields",
      "opcode": "fc00058e",
      "form": "XFL",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "FM",
          "conditional": false
        },
        {
          "field": "FB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "FPSCR",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mtfsf[Rc] [FM], [FB]"
    },
    {
      "mnemonic": "mtfsfix",
      "description": "Move to FPSCR Field Immediate",
      "opcode": "fc00010c",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "IMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CRFD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mtfsfi[Rc] [CRFD], [IMM]"
    },
    {
      "mnemonic": "mtmsr",
      "description": "Move to Machine State Register",
      "opcode": "7c000124",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "MSR",
          "conditional": false
        }
      ],
      "disassembly": "mtmsr [RS]"
    },
    {
      "mnemonic": "mtmsrd",
      "description": "Move to Machine State Register Doubleword",
      "opcode": "7c000164",
      "form": "X",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "MSR",
          "conditional": false
        }
      ],
      "disassembly": "mtmsrd [RS]"
    },
    {
      "mnemonic": "mtspr",
      "description": "Move to Special-Purpose Register",
      "opcode": "7c0003a6",
      "form": "XFX",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "SPR",
          "conditional": false
        }
      ],
      "disassembly": "mtspr [SPR], [RS]"
    },
    {
      "mnemonic": "mulhdx",
      "description": "Multiply High Doubleword",
      "opcode": "7c000092",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mulhd[Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "mulhdux",
      "description": "Multiply High Doubleword Unsigned",
      "opcode": "7c000012",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mulhdu[Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "mulhwx",
      "description": "Multiply High Word",
      "opcode": "7c000096",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mulhw[Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "mulhwux",
      "description": "Multiply High Word Unsigned",
      "opcode": "7c000016",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "mulhwu[Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "mulldx",
      "description": "Multiply Low Doubleword",
      "opcode": "7c0001d2",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        }
      ],
      "disassembly": "mulld[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "mulli",
      "description": "Multiply Low Immediate",
      "opcode": "1c000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        }
      ],
      "disassembly": "mulli [RD], [RA], [SIMM]"
    },
    {
      "mnemonic": "mullwx",
      "description": "Multiply Low Word",
      "opcode": "7c0001d6",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        }
      ],
      "disassembly": "mullw[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "nandx",
      "description": "NAND",
      "opcode": "7c0003b8",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "nand[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "negx",
      "description": "Negate",
      "opcode": "7c0000d0",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        }
      ],
      "disassembly": "neg[OE][Rc] [RD], [RA]"
    },
    {
      "mnemonic": "norx",
      "description": "NOR",
      "opcode": "7c0000f8",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "nor[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "orx",
      "description": "OR",
      "opcode": "7c000378",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "or[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "orcx",
      "description": "OR with Complement",
      "opcode": "7c000338",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "orc[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "ori",
      "description": "OR Immediate",
      "opcode": "60000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "ori [RA], [RS], [UIMM]"
    },
    {
      "mnemonic": "oris",
      "description": "OR Immediate Shifted",
      "opcode": "64000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "oris [RA], [RS], [UIMM]"
    },
    {
      "mnemonic": "rldclx",
      "description": "Rotate Left Doubleword then Clear Left",
      "opcode": "78000010",
      "form": "MDS",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rldcl[Rc] [RA], [RS], [RB], [MB]"
    },
    {
      "mnemonic": "rldcrx",
      "description": "Rotate Left Doubleword then Clear Right",
      "opcode": "78000012",
      "form": "MDS",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        },
        {
          "field": "ME",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rldcr[Rc] [RA], [RS], [RB], [ME]"
    },
    {
      "mnemonic": "rldicx",
      "description": "Rotate Left Doubleword Immediate then Clear",
      "opcode": "78000008",
      "form": "MD",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rldic[Rc] [RA], [RS], [SH], [MB]"
    },
    {
      "mnemonic": "rldiclx",
      "description": "Rotate Left Doubleword Immediate then Clear Left",
      "opcode": "78000000",
      "form": "MD",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rldicl[Rc] [RA], [RS], [SH], [MB]"
    },
    {
      "mnemonic": "rldicrx",
      "description": "Rotate Left Doubleword Immediate then Clear Right",
      "opcode": "78000004",
      "form": "MD",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        },
        {
          "field": "ME",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rldicr[Rc] [RA], [RS], [SH], [ME]"
    },
    {
      "mnemonic": "rldimix",
      "description": "Rotate Left Doubleword Immediate then Mask Insert",
      "opcode": "7800000C",
      "form": "MD",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rldimi[Rc] [RA], [RS], [SH], [MB]"
    },
    {
      "mnemonic": "rlwimix",
      "description": "Rotate Left Word Immediate then Mask Insert",
      "opcode": "50000000",
      "form": "M",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        },
        {
          "field": "ME",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rlwimi[Rc] [RA], [RS], [SH], [MB], [ME]"
    },
    {
      "mnemonic": "rlwinmx",
      "description": "Rotate Left Word Immediate then AND with Mask",
      "opcode": "54000000",
      "form": "M",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        },
        {
          "field": "ME",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rlwinm[Rc] [RA], [RS], [SH], [MB], [ME]"
    },
    {
      "mnemonic": "rlwnmx",
      "description": "Rotate Left Word then AND with Mask",
      "opcode": "5c000000",
      "form": "M",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        },
        {
          "field": "MB",
          "conditional": false
        },
        {
          "field": "ME",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "rlwnm[Rc] [RA], [RS], [RB], [MB], [ME]"
    },
    {
      "mnemonic": "sc",
      "description": "System Call",
      "opcode": "44000002",
      "form": "SC",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "LEV",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "sc [LEV]"
    },
    {
      "mnemonic": "sldx",
      "description": "Shift Left Doubleword",
      "opcode": "7c000036",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "sld[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "slwx",
      "description": "Shift Left Word",
      "opcode": "7c000030",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "slw[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "sradx",
      "description": "Shift Right Algebraic Doubleword",
      "opcode": "7c000634",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "srad[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "sradix",
      "description": "Shift Right Algebraic Doubleword Immediate",
      "opcode": "7c000674",
      "form": "XS",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "sradi[Rc] [RA], [RS], [SH]"
    },
    {
      "mnemonic": "srawx",
      "description": "Shift Right Algebraic Word",
      "opcode": "7c000630",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "sraw[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "srawix",
      "description": "Shift Right Algebraic Word Immediate",
      "opcode": "7c000670",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "SH",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "srawi[Rc] [RA], [RS], [SH]"
    },
    {
      "mnemonic": "srdx",
      "description": "Shift Right Doubleword",
      "opcode": "7c000436",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "srd[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "srwx",
      "description": "Shift Right Word",
      "opcode": "7c000430",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "srw[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "stb",
      "description": "Store Byte",
      "opcode": "98000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stb [RS], [d]([RA0])"
    },
    {
      "mnemonic": "stbu",
      "description": "Store Byte with Update",
      "opcode": "9c000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stbu [RS], [d]([RA])"
    },
    {
      "mnemonic": "stbux",
      "description": "Store Byte with Update Indexed",
      "opcode": "7c0001ee",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stbux [RS], [RA], [RB]"
    },
    {
      "mnemonic": "stbx",
      "description": "Store Byte Indexed",
      "opcode": "7c0001ae",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stbx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "std",
      "description": "Store Doubleword",
      "opcode": "f8000000",
      "form": "DS",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "ds",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "std [RS], [ds]([RA0])"
    },
    {
      "mnemonic": "stdbrx",
      "description": "Store Doubleword Byte-Reverse Indexed",
      "opcode": "7c000528",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stdbrx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "stdcx",
      "description": "Store Doubleword Conditional Indexed",
      "opcode": "7c0001ad",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "disassembly": "stdcx. [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "stdu",
      "description": "Store Doubleword with Update",
      "opcode": "f8000001",
      "form": "DS",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "ds",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stdu [RS], [ds]([RA])"
    },
    {
      "mnemonic": "stdux",
      "description": "Store Doubleword with Update Indexed",
      "opcode": "7c00016a",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stdux [RS], [RA], [RB]"
    },
    {
      "mnemonic": "stdx",
      "description": "Store Doubleword Indexed",
      "opcode": "7c00012a",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stdx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "stfd",
      "description": "Store Floating-Point Double",
      "opcode": "d8000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stfd [FS], [d]([RA0])"
    },
    {
      "mnemonic": "stfdu",
      "description": "Store Floating-Point Double with Update",
      "opcode": "dc000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stfdu [FS], [d]([RA])"
    },
    {
      "mnemonic": "stfdux",
      "description": "Store Floating-Point Double with Update Indexed",
      "opcode": "7c0005ee",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stfdux [FS], [RA], [RB]"
    },
    {
      "mnemonic": "stfdx",
      "description": "Store Floating-Point Double Indexed",
      "opcode": "7c0005ae",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stfdx [FS], [RA0], [RB]"
    },
    {
      "mnemonic": "stfiwx",
      "description": "Store Floating-Point as Integer Word Indexed",
      "opcode": "7c0007ae",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stfiwx [FS], [RA0], [RB]"
    },
    {
      "mnemonic": "stfs",
      "description": "Store Floating-Point Single",
      "opcode": "d0000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stfs [FS], [d]([RA0])"
    },
    {
      "mnemonic": "stfsu",
      "description": "Store Floating-Point Single with Update",
      "opcode": "d4000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stfsu [FS], [d]([RA])"
    },
    {
      "mnemonic": "stfsux",
      "description": "Store Floating-Point Single with Update Indexed",
      "opcode": "7c00056e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stfsux [FS], [RA], [RB]"
    },
    {
      "mnemonic": "stfsx",
      "description": "Store Floating-Point Single Indexed",
      "opcode": "7c00052e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "FS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stfsx [FS], [RA], [RB]"
    },
    {
      "mnemonic": "sth",
      "description": "Store Half Word",
      "opcode": "b0000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "sth [RS], [d]([RA0])"
    },
    {
      "mnemonic": "sthbrx",
      "description": "Store Half Word Byte-Reverse Indexed",
      "opcode": "7c00072c",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "sthbrx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "sthu",
      "description": "Store Half Word with Update",
      "opcode": "b4000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "sthu [RS], [d]([RA])"
    },
    {
      "mnemonic": "sthux",
      "description": "Store Half Word with Update Indexed",
      "opcode": "7c00036e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "sthux [RS], [RA], [RB]"
    },
    {
      "mnemonic": "sthx",
      "description": "Store Half Word Indexed",
      "opcode": "7c00032e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "sthx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "stmw",
      "description": "Store Multiple Word",
      "opcode": "bc000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": ""
    },
    {
      "mnemonic": "stswi",
      "description": "Store String Word Immediate",
      "opcode": "7c0005aa",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": ""
    },
    {
      "mnemonic": "stswx",
      "description": "Store String Word Indexed",
      "opcode": "7c00052a",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": ""
    },
    {
      "mnemonic": "stw",
      "description": "Store Word",
      "opcode": "90000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stw [RS], [d]([RA0])"
    },
    {
      "mnemonic": "stwbrx",
      "description": "Store Word Byte-Reverse Indexed",
      "opcode": "7c00052c",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stwbrx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "stwcx",
      "description": "Store Word Conditional Indexed",
      "opcode": "7c00012d",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "CR",
          "conditional": false
        }
      ],
      "disassembly": "stwcx. [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "stwu",
      "description": "Store Word with Update",
      "opcode": "94000000",
      "form": "D",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "d",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stwu [RS], [d]([RA])"
    },
    {
      "mnemonic": "stwux",
      "description": "Store Word with Update Indexed",
      "opcode": "7c00016e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "stwux [RS], [RA], [RB]"
    },
    {
      "mnemonic": "stwx",
      "description": "Store Word Indexed",
      "opcode": "7c00012e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stwx [RS], [RA0], [RB]"
    },
    {
      "mnemonic": "subfx",
      "description": "Subtract From",
      "opcode": "7c000050",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        }
      ],
      "disassembly": "subf[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "subfcx",
      "description": "Subtract From Carrying",
      "opcode": "7c000010",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        }
      ],
      "disassembly": "subfc[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "subfex",
      "description": "Subtract From Extended",
      "opcode": "7c000110",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        }
      ],
      "disassembly": "subfe[OE][Rc] [RD], [RA], [RB]"
    },
    {
      "mnemonic": "subficx",
      "description": "Subtract From Immediate Carrying",
      "opcode": "20000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "subfic [RD], [RA], [SIMM]"
    },
    {
      "mnemonic": "subfmex",
      "description": "Subtract From Minus One Extended",
      "opcode": "7c0001d0",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "subfme[OE][Rc] [RD], [RA]"
    },
    {
      "mnemonic": "subfzex",
      "description": "Subtract From Zero Extended",
      "opcode": "7c000190",
      "form": "XO",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        },
        {
          "field": "OE",
          "conditional": true
        },
        {
          "field": "CA",
          "conditional": false
        }
      ],
      "disassembly": "subfze[OE][Rc] [RD], [RA]"
    },
    {
      "mnemonic": "sync",
      "description": "Synchronize",
      "opcode": "7c0004ac",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [],
      "outputs": [],
      "disassembly": "sync"
    },
    {
      "mnemonic": "td",
      "description": "Trap Doubleword",
      "opcode": "7c000088",
      "form": "X",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "TO",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "td [TO], [RA], [RB]"
    },
    {
      "mnemonic": "tdi",
      "description": "Trap Doubleword Immediate",
      "opcode": "08000000",
      "form": "D",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "TO",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "tdi [TO], [RA], [SIMM]"
    },
    {
      "mnemonic": "tw",
      "description": "Trap Word",
      "opcode": "7c000008",
      "form": "X",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "TO",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "tw [TO], [RA], [RB]"
    },
    {
      "mnemonic": "twi",
      "description": "Trap Word Immediate",
      "opcode": "0c000000",
      "form": "D",
      "group": "b",
      "category": "Branch / System",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_control.cc",
      "inputs": [
        {
          "field": "TO",
          "conditional": false
        },
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "tw [TO], [RA], [SIMM]"
    },
    {
      "mnemonic": "xorx",
      "description": "XOR",
      "opcode": "7c000278",
      "form": "X",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "xor[Rc] [RA], [RS], [RB]"
    },
    {
      "mnemonic": "xori",
      "description": "XOR Immediate",
      "opcode": "68000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "xori [RA], [RS], [UIMM]"
    },
    {
      "mnemonic": "xoris",
      "description": "XOR Immediate Shifted",
      "opcode": "6c000000",
      "form": "D",
      "group": "i",
      "category": "Integer / ALU",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_alu.cc",
      "inputs": [
        {
          "field": "RS",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "RA",
          "conditional": false
        }
      ],
      "disassembly": "xoris [RA], [RS], [UIMM]"
    },
    {
      "mnemonic": "lvebx",
      "description": "Load Vector Element Byte Indexed",
      "opcode": "7c00000e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvebx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvehx",
      "description": "Load Vector Element Half Word Indexed",
      "opcode": "7c00004e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvehx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvewx",
      "description": "Load Vector Element Word Indexed",
      "opcode": "7c00008e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvewx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvewx128",
      "description": "Load Vector Element Word Indexed 128",
      "opcode": "10000083",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvewx128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvsl",
      "description": "Load Vector for Shift Left Indexed",
      "opcode": "7c00000c",
      "form": "X",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvsl [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvsl128",
      "description": "Load Vector for Shift Left Indexed 128",
      "opcode": "10000003",
      "form": "VX128_1",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvsl128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvsr",
      "description": "Load Vector for Shift Right Indexed",
      "opcode": "7c00004c",
      "form": "X",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvsr [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvsr128",
      "description": "Load Vector for Shift Right Indexed 128",
      "opcode": "10000043",
      "form": "VX128_1",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvsr128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvx",
      "description": "Load Vector Indexed",
      "opcode": "7c0000ce",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvx128",
      "description": "Load Vector Indexed 128",
      "opcode": "100000C3",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvx128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvxl",
      "description": "Load Vector Indexed LRU",
      "opcode": "7c0002ce",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvslx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvxl128",
      "description": "Load Vector Indexed LRU 128",
      "opcode": "100002C3",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvxl128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvlx",
      "description": "Load Vector Left Indexed",
      "opcode": "7C00040E",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvlx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvlx128",
      "description": "Load Vector Left Indexed 128",
      "opcode": "10000403",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvlx128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvlxl",
      "description": "Load Vector Left Indexed LRU",
      "opcode": "7C00060E",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvlxl [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvlxl128",
      "description": "Load Vector Left Indexed LRU 128",
      "opcode": "10000603",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvlxl128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvrx",
      "description": "Load Vector Right Indexed",
      "opcode": "7C00044E",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvrx [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvrx128",
      "description": "Load Vector Right Indexed 128",
      "opcode": "10000443",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvrx128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvrxl",
      "description": "Load Vector Right Indexed LRU",
      "opcode": "7C00064E",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvrxl [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "lvrxl128",
      "description": "Load Vector Right Indexed LRU 128",
      "opcode": "10000643",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "lvrxl128 [VD], [RA0], [RB]"
    },
    {
      "mnemonic": "mfvscr",
      "description": "Move from VSCR",
      "opcode": "10000604",
      "form": "VX",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": ""
    },
    {
      "mnemonic": "mtvscr",
      "description": "Move to VSCR",
      "opcode": "10000644",
      "form": "VX",
      "group": "c",
      "category": "Condition Register / SPR",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": ""
    },
    {
      "mnemonic": "stvebx",
      "description": "Store Vector Element Byte Indexed",
      "opcode": "7c00010e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvebx [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvehx",
      "description": "Store Vector Element Half Word Indexed",
      "opcode": "7c00014e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvehx [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvewx",
      "description": "Store Vector Element Word Indexed",
      "opcode": "7c00018e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvewx [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvewx128",
      "description": "Store Vector Element Word Indexed 128",
      "opcode": "10000183",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvewx128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvx",
      "description": "Store Vector Indexed",
      "opcode": "7c0001ce",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvx [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvx128",
      "description": "Store Vector Indexed 128",
      "opcode": "100001c3",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvx128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvxl",
      "description": "Store Vector Indexed LRU",
      "opcode": "7c0003ce",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvxl [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvxl128",
      "description": "Store Vector Indexed LRU 128",
      "opcode": "100003c3",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvxl128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvlx",
      "description": "Store Vector Left Indexed",
      "opcode": "7c00050e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvlx [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvlx128",
      "description": "Store Vector Left Indexed 128",
      "opcode": "10000503",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvlx128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvlxl",
      "description": "Store Vector Left Indexed LRU",
      "opcode": "7c00070e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvlxl [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvlxl128",
      "description": "Store Vector Left Indexed LRU 128",
      "opcode": "10000703",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvlxl128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvrx",
      "description": "Store Vector Right Indexed",
      "opcode": "7c00054e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvrx [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvrx128",
      "description": "Store Vector Right Indexed 128",
      "opcode": "10000543",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvrx128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvrxl",
      "description": "Store Vector Right Indexed LRU",
      "opcode": "7c00074e",
      "form": "X",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvrxl [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "stvrxl128",
      "description": "Store Vector Right Indexed LRU 128",
      "opcode": "10000743",
      "form": "VX128_1",
      "group": "m",
      "category": "Memory (Load/Store/Cache)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_memory.cc",
      "inputs": [
        {
          "field": "VS",
          "conditional": false
        },
        {
          "field": "RA0",
          "conditional": false
        },
        {
          "field": "RB",
          "conditional": false
        }
      ],
      "outputs": [],
      "disassembly": "stvrxl128 [VS], [RA0], [RB]"
    },
    {
      "mnemonic": "vaddcuw",
      "description": "Vector Add Carryout Unsigned Word",
      "opcode": "10000180",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vaddcuw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddfp",
      "description": "Vector Add Floating Point",
      "opcode": "1000000A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vaddfp [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddfp128",
      "description": "Vector128 Add Floating Point",
      "opcode": "14000010",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vaddfp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddsbs",
      "description": "Vector Add Signed Byte Saturate",
      "opcode": "10000300",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vaddsbs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddshs",
      "description": "Vector Add Signed Half Word Saturate",
      "opcode": "10000340",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vaddshs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddsws",
      "description": "Vector Add Signed Word Saturate",
      "opcode": "10000380",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vaddsws [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddubm",
      "description": "Vector Add Unsigned Byte Modulo",
      "opcode": "10000000",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vaddubm [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vaddubs",
      "description": "Vector Add Unsigned Byte Saturate",
      "opcode": "10000200",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vaddubs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vadduhm",
      "description": "Vector Add Unsigned Half Word Modulo",
      "opcode": "10000040",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vadduhm [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vadduhs",
      "description": "Vector Add Unsigned Half Word Saturate",
      "opcode": "10000240",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vadduhs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vadduwm",
      "description": "Vector Add Unsigned Word Modulo",
      "opcode": "10000080",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vadduwm [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vadduws",
      "description": "Vector Add Unsigned Word Saturate",
      "opcode": "10000280",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vadduws [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vand",
      "description": "Vector Logical AND",
      "opcode": "10000404",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vand [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vand128",
      "description": "Vector128 Logical AND",
      "opcode": "14000210",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vand128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vandc",
      "description": "Vector Logical AND with Complement",
      "opcode": "10000444",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vandc [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vandc128",
      "description": "Vector128 Logical AND with Complement",
      "opcode": "14000250",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vandc128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vavgsb",
      "description": "Vector Average Signed Byte",
      "opcode": "10000502",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vavgsb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vavgsh",
      "description": "Vector Average Signed Half Word",
      "opcode": "10000542",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vavgsh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vavgsw",
      "description": "Vector Average Signed Word",
      "opcode": "10000582",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vavgsw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vavgub",
      "description": "Vector Average Unsigned Byte",
      "opcode": "10000402",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vavgub [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vavguh",
      "description": "Vector Average Unsigned Half Word",
      "opcode": "10000442",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vavguh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vavguw",
      "description": "Vector Average Unsigned Word",
      "opcode": "10000482",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vavguw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcfsx",
      "description": "Vector Convert from Signed Fixed-Point Word",
      "opcode": "1000034A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vcfsx [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vcfux",
      "description": "Vector Convert from Unsigned Fixed-Point Word",
      "opcode": "1000030A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vcfux [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vcmpbfp",
      "description": "Vector Compare Bounds Floating Point",
      "opcode": "100003C6",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpbfp[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpbfp128",
      "description": "Vector128 Compare Bounds Floating Point",
      "opcode": "18000180",
      "form": "VX128_R",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpbfp128[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpeqfp",
      "description": "Vector Compare Equal-to Floating Point",
      "opcode": "100000C6",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpeqfp[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpeqfp128",
      "description": "Vector128 Compare Equal-to Floating Point",
      "opcode": "18000000",
      "form": "VX128_R",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpeqfp128[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpequb",
      "description": "Vector Compare Equal-to Unsigned Byte",
      "opcode": "10000006",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpequb[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpequh",
      "description": "Vector Compare Equal-to Unsigned Half Word",
      "opcode": "10000046",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpequh[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpequw",
      "description": "Vector Compare Equal-to Unsigned Word",
      "opcode": "10000086",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpequw[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpequw128",
      "description": "Vector128 Compare Equal-to Unsigned Word",
      "opcode": "18000200",
      "form": "VX128_R",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpequw128[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgefp",
      "description": "Vector Compare Greater-Than-or-Equal-to Floating Point",
      "opcode": "100001C6",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgefp[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgefp128",
      "description": "Vector128 Compare Greater-Than-or-Equal-to Floating Point",
      "opcode": "18000080",
      "form": "VX128_R",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgefp128[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtfp",
      "description": "Vector Compare Greater-Than Floating Point",
      "opcode": "100002C6",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtfp[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtfp128",
      "description": "Vector128 Compare Greater-Than Floating-Point",
      "opcode": "18000100",
      "form": "VX128_R",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtfp128[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtsb",
      "description": "Vector Compare Greater-Than Signed Byte",
      "opcode": "10000306",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtsb[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtsh",
      "description": "Vector Compare Greater-Than Signed Half Word",
      "opcode": "10000346",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtsh[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtsw",
      "description": "Vector Compare Greater-Than Signed Word",
      "opcode": "10000386",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtsw[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtub",
      "description": "Vector Compare Greater-Than Unsigned Byte",
      "opcode": "10000206",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtub[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtuh",
      "description": "Vector Compare Greater-Than Unsigned Half Word",
      "opcode": "10000246",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtuh[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vcmpgtuw",
      "description": "Vector Compare Greater-Than Unsigned Word",
      "opcode": "10000286",
      "form": "VC",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "CR",
          "conditional": true
        }
      ],
      "disassembly": "vcmpgtuw[Rc] [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vctsxs",
      "description": "Vector Convert to Signed Fixed-Point Word Saturate",
      "opcode": "100003CA",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vctsxs [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vctuxs",
      "description": "Vector Convert to Unsigned Fixed-Point Word Saturate",
      "opcode": "1000038A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vctuxs [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vexptefp",
      "description": "Vector 2 Raised to the Exponent Estimate Floating Point",
      "opcode": "1000018A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vexptefp [VD], [VB]"
    },
    {
      "mnemonic": "vexptefp128",
      "description": "Vector128 Log2 Estimate Floating Point",
      "opcode": "180006B0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vexptefp128 [VD], [VB]"
    },
    {
      "mnemonic": "vlogefp",
      "description": "Vector Log2 Estimate Floating Point",
      "opcode": "100001CA",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vlogefp [VD], [VB]"
    },
    {
      "mnemonic": "vlogefp128",
      "description": "Vector128 Log2 Estimate Floating Point",
      "opcode": "180006F0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vlogefp128 [VD], [VB]"
    },
    {
      "mnemonic": "vmaddfp",
      "description": "Vector Multiply-Add Floating Point",
      "opcode": "1000002E",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaddfp [VD], [VA], [VC], [VB]"
    },
    {
      "mnemonic": "vmaddfp128",
      "description": "Vector128 Multiply Add Floating Point",
      "opcode": "140000D0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaddfp128 [VD], [VA], [VB], [VD]"
    },
    {
      "mnemonic": "vmaxfp",
      "description": "Vector Maximum Floating Point",
      "opcode": "1000040A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxfp [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxfp128",
      "description": "Vector128 Maximum Floating Point",
      "opcode": "18000280",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxfp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxsb",
      "description": "Vector Maximum Signed Byte",
      "opcode": "10000102",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxsb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxsh",
      "description": "Vector Maximum Signed Half Word",
      "opcode": "10000142",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxsh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxsw",
      "description": "Vector Maximum Signed Word",
      "opcode": "10000182",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxsw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxub",
      "description": "Vector Maximum Unsigned Byte",
      "opcode": "10000002",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxub [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxuh",
      "description": "Vector Maximum Unsigned Half Word",
      "opcode": "10000042",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxuh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaxuw",
      "description": "Vector Maximum Unsigned Word",
      "opcode": "10000082",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaxuw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmhaddshs",
      "description": "Vector Multiply-High and Add Signed Signed Half Word Saturate",
      "opcode": "10000020",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vmhaddshs [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmhraddshs",
      "description": "Vector Multiply-High Round and Add Signed Signed Half Word Saturate",
      "opcode": "10000021",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vmhraddshs [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vminfp",
      "description": "Vector Minimum Floating Point",
      "opcode": "1000044A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminfp [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminfp128",
      "description": "Vector128 Minimum Floating Point",
      "opcode": "180002C0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminfp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminsb",
      "description": "Vector Minimum Signed Byte",
      "opcode": "10000302",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminsb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminsh",
      "description": "Vector Minimum Signed Half Word",
      "opcode": "10000342",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminsh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminsw",
      "description": "Vector Minimum Signed Word",
      "opcode": "10000382",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminsw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminub",
      "description": "Vector Minimum Unsigned Byte",
      "opcode": "10000202",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminub [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminuh",
      "description": "Vector Minimum Unsigned Half Word",
      "opcode": "10000242",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminuh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vminuw",
      "description": "Vector Minimum Unsigned Word",
      "opcode": "10000282",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vminuw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmladduhm",
      "description": "Vector Multiply-Low and Add Unsigned Half Word Modulo",
      "opcode": "10000022",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmladduhm [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmrghb",
      "description": "Vector Merge High Byte",
      "opcode": "1000000C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrghb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrghh",
      "description": "Vector Merge High Half Word",
      "opcode": "1000004C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrghh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrghw",
      "description": "Vector Merge High Word",
      "opcode": "1000008C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrghw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrghw128",
      "description": "Vector128 Merge High Word",
      "opcode": "18000300",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrghw128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrglb",
      "description": "Vector Merge Low Byte",
      "opcode": "1000010C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrglb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrglh",
      "description": "Vector Merge Low Half Word",
      "opcode": "1000014C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrglh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrglw",
      "description": "Vector Merge Low Word",
      "opcode": "1000018C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrglw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmrglw128",
      "description": "Vector128 Merge Low Word",
      "opcode": "18000340",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmrglw128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmsummbm",
      "description": "Vector Multiply-Sum Mixed-Sign Byte Modulo",
      "opcode": "10000025",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmsummbm [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmsumshm",
      "description": "Vector Multiply-Sum Signed Half Word Modulo",
      "opcode": "10000028",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmsumshm [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmsumshs",
      "description": "Vector Multiply-Sum Signed Half Word Saturate",
      "opcode": "10000029",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vmsumshs [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmsumubm",
      "description": "Vector Multiply-Sum Unsigned Byte Modulo",
      "opcode": "10000024",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmsumubm [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmsumuhm",
      "description": "Vector Multiply-Sum Unsigned Half Word Modulo",
      "opcode": "10000026",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmsumuhm [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmsumuhs",
      "description": "Vector Multiply-Sum Unsigned Half Word Saturate",
      "opcode": "10000027",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vmsumuhs [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vmulesb",
      "description": "Vector Multiply Even Signed Byte",
      "opcode": "10000308",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmulesb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmulesh",
      "description": "Vector Multiply Even Signed Half Word",
      "opcode": "10000348",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmulesh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmuleub",
      "description": "Vector Multiply Even Unsigned Byte",
      "opcode": "10000208",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmuleub [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmuleuh",
      "description": "Vector Multiply Even Unsigned Half Word",
      "opcode": "10000248",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmuleuh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmulosb",
      "description": "Vector Multiply Odd Signed Byte",
      "opcode": "10000108",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmulosb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmulosh",
      "description": "Vector Multiply Odd Signed Half Word",
      "opcode": "10000148",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmulosh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmuloub",
      "description": "Vector Multiply Odd Unsigned Byte",
      "opcode": "10000008",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmuloub [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmulouh",
      "description": "Vector Multiply Odd Unsigned Half Word",
      "opcode": "10000048",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmulouh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vnmsubfp",
      "description": "Vector Negative Multiply-Subtract Floating Point",
      "opcode": "1000002F",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vnmsubfp [VD], [VA], [VC], [VB]"
    },
    {
      "mnemonic": "vnmsubfp128",
      "description": "Vector128 Negative Multiply-Subtract Floating Point",
      "opcode": "14000150",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vnmsubfp128 [VD], [VA], [VD], [VB]"
    },
    {
      "mnemonic": "vnor",
      "description": "Vector Logical NOR",
      "opcode": "10000504",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vnor [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vnor128",
      "description": "Vector128 Logical NOR",
      "opcode": "14000290",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vnor128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vor",
      "description": "Vector Logical OR",
      "opcode": "10000484",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vor [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vor128",
      "description": "Vector128 Logical OR",
      "opcode": "140002D0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vor128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vperm",
      "description": "Vector Permute",
      "opcode": "1000002B",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vperm [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vperm128",
      "description": "Vector128 Permute",
      "opcode": "14000000",
      "form": "VX128_2",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vperm128 [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vpkpx",
      "description": "Vector Pack Pixel",
      "opcode": "1000030E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vpkpx [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkshss",
      "description": "Vector Pack Signed Half Word Signed Saturate",
      "opcode": "1000018E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkshss [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkshss128",
      "description": "Vector128 Pack Signed Half Word Signed Saturate",
      "opcode": "14000200",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkshss128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkshus",
      "description": "Vector Pack Signed Half Word Unsigned Saturate",
      "opcode": "1000010E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkshus [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkshus128",
      "description": "Vector128 Pack Signed Half Word Unsigned Saturate",
      "opcode": "14000240",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkshus128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkswss",
      "description": "Vector Pack Signed Word Signed Saturate",
      "opcode": "100001CE",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkswss [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkswss128",
      "description": "Vector128 Pack Signed Word Signed Saturate",
      "opcode": "14000280",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkswss128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkswus",
      "description": "Vector Pack Signed Word Unsigned Saturate",
      "opcode": "1000014E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkswus [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkswus128",
      "description": "Vector128 Pack Signed Word Unsigned Saturate",
      "opcode": "140002C0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkswus128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuhum",
      "description": "Vector Pack Unsigned Half Word Unsigned Modulo",
      "opcode": "1000000E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vpkuhum [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuhum128",
      "description": "Vector128 Pack Unsigned Half Word Unsigned Modulo",
      "opcode": "14000300",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vpkuhum128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuhus",
      "description": "Vector Pack Unsigned Half Word Unsigned Saturate",
      "opcode": "1000008E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkuhus [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuhus128",
      "description": "Vector128 Pack Unsigned Half Word Unsigned Saturate",
      "opcode": "14000340",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkuhus128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuwum",
      "description": "Vector Pack Unsigned Word Unsigned Modulo",
      "opcode": "1000004E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vpkuwum [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuwum128",
      "description": "Vector128 Pack Unsigned Word Unsigned Modulo",
      "opcode": "14000380",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vpkuwum128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuwus",
      "description": "Vector Pack Unsigned Word Unsigned Saturate",
      "opcode": "100000CE",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkuwus [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpkuwus128",
      "description": "Vector128 Pack Unsigned Word Unsigned Saturate",
      "opcode": "140003C0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vpkuwus128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vrefp",
      "description": "Vector Reciprocal Estimate Floating Point",
      "opcode": "1000010A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrefp [VD], [VB]"
    },
    {
      "mnemonic": "vrefp128",
      "description": "Vector128 Reciprocal Estimate Floating Point",
      "opcode": "18000630",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrefp128 [VD], [VB]"
    },
    {
      "mnemonic": "vrfim",
      "description": "Vector Round to Floating-Point Integer toward -Infinity",
      "opcode": "100002CA",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfim [VD], [VB]"
    },
    {
      "mnemonic": "vrfim128",
      "description": "Vector128 Round to Floating-Point Integer toward -Infinity",
      "opcode": "18000330",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfim128 [VD], [VB]"
    },
    {
      "mnemonic": "vrfin",
      "description": "Vector Round to Floating-Point Integer Nearest",
      "opcode": "1000020A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfin [VD], [VB]"
    },
    {
      "mnemonic": "vrfin128",
      "description": "Vector128 Round to Floating-Point Integer Nearest",
      "opcode": "18000370",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfin128 [VD], [VB]"
    },
    {
      "mnemonic": "vrfip",
      "description": "Vector Round to Floating-Point Integer toward +Infinity",
      "opcode": "1000028A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfip [VD], [VB]"
    },
    {
      "mnemonic": "vrfip128",
      "description": "Vector128 Round to Floating-Point Integer toward +Infinity",
      "opcode": "180003B0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfip128 [VD], [VB]"
    },
    {
      "mnemonic": "vrfiz",
      "description": "Vector Round to Floating-Point Integer toward Zero",
      "opcode": "1000024A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfiz [VD], [VB]"
    },
    {
      "mnemonic": "vrfiz128",
      "description": "Vector128 Round to Floating-Point Integer toward Zero",
      "opcode": "180003F0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrfiz128 [VD], [VB]"
    },
    {
      "mnemonic": "vrlb",
      "description": "Vector Rotate Left Integer Byte",
      "opcode": "10000004",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrlb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vrlh",
      "description": "Vector Rotate Left Integer Half Word",
      "opcode": "10000044",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrlh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vrlw",
      "description": "Vector Rotate Left Integer Word",
      "opcode": "10000084",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrlw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vrlw128",
      "description": "Vector128 Rotate Left Word",
      "opcode": "18000050",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrlw128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vrsqrtefp",
      "description": "Vector Reciprocal Square Root Estimate Floating Point",
      "opcode": "1000014A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrsqrtefp [VD], [VB]"
    },
    {
      "mnemonic": "vrsqrtefp128",
      "description": "Vector128 Reciprocal Square Root Estimate Floating Point",
      "opcode": "18000670",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrsqrtefp128 [VD], [VB]"
    },
    {
      "mnemonic": "vsel",
      "description": "Vector Conditional Select",
      "opcode": "1000002A",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VC",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsel [VD], [VA], [VB], [VC]"
    },
    {
      "mnemonic": "vsel128",
      "description": "Vector128 Conditional Select",
      "opcode": "14000350",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsel128 [VD], [VA], [VB], [VD]"
    },
    {
      "mnemonic": "vsl",
      "description": "Vector Shift Left",
      "opcode": "100001C4",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsl [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vslb",
      "description": "Vector Shift Left Integer Byte",
      "opcode": "10000104",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vslb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsldoi",
      "description": "Vector Shift Left Double by Octet Immediate",
      "opcode": "1000002C",
      "form": "VA",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "SHB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsldoi [VD], [VA], [VB], [SHB]"
    },
    {
      "mnemonic": "vsldoi128",
      "description": "Vector128 Shift Left Double by Octet Immediate",
      "opcode": "10000010",
      "form": "VX128_5",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "SHB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsldoi128 [VD], [VA], [VB], [SHB]"
    },
    {
      "mnemonic": "vslh",
      "description": "Vector Shift Left Integer Half Word",
      "opcode": "10000144",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vslh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vslo",
      "description": "Vector Shift Left by Octet",
      "opcode": "1000040C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vslo [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vslo128",
      "description": "Vector128 Shift Left Octet",
      "opcode": "14000390",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vslo128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vslw",
      "description": "Vector Shift Left Integer Word",
      "opcode": "10000184",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vslw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vslw128",
      "description": "Vector128 Shift Left Integer Word",
      "opcode": "180000D0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vslw128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vspltb",
      "description": "Vector Splat Byte",
      "opcode": "1000020C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltb [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vsplth",
      "description": "Vector Splat Half Word",
      "opcode": "1000024C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsplth [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vspltisb",
      "description": "Vector Splat Immediate Signed Byte",
      "opcode": "1000030C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltisb [VD], [SIMM]"
    },
    {
      "mnemonic": "vspltish",
      "description": "Vector Splat Immediate Signed Half Word",
      "opcode": "1000034C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltish [VD], [SIMM]"
    },
    {
      "mnemonic": "vspltisw",
      "description": "Vector Splat Immediate Signed Word",
      "opcode": "1000038C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltisw [VD], [SIMM]"
    },
    {
      "mnemonic": "vspltisw128",
      "description": "Vector128 Splat Immediate Signed Word",
      "opcode": "18000770",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "SIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltisw128 [VD], [SIMM]"
    },
    {
      "mnemonic": "vspltw",
      "description": "Vector Splat Word",
      "opcode": "1000028C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltw [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vspltw128",
      "description": "Vector128 Splat Word",
      "opcode": "18000730",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vspltw128 [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vsr",
      "description": "Vector Shift Right",
      "opcode": "100002C4",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsr [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsrab",
      "description": "Vector Shift Right Algebraic Byte",
      "opcode": "10000304",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsrab [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsrah",
      "description": "Vector Shift Right Algebraic Half Word",
      "opcode": "10000344",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsrah [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsraw",
      "description": "Vector Shift Right Algebraic Word",
      "opcode": "10000384",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsraw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsraw128",
      "description": "Vector128 Shift Right Arithmetic Word",
      "opcode": "18000150",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsraw128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsrb",
      "description": "Vector Shift Right Byte",
      "opcode": "10000204",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsrb [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsrh",
      "description": "Vector Shift Right Half Word",
      "opcode": "10000244",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsrh [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsro",
      "description": "Vector Shift Right Octet",
      "opcode": "1000044C",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsro [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsro128",
      "description": "Vector128 Shift Right Octet",
      "opcode": "140003D0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsro128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsrw",
      "description": "Vector Shift Right Word",
      "opcode": "10000284",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsrw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsrw128",
      "description": "Vector128 Shift Right Word",
      "opcode": "180001D0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsrw128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubcuw",
      "description": "Vector Subtract Carryout Unsigned Word",
      "opcode": "10000580",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsubcuw [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubfp",
      "description": "Vector Subtract Floating Point",
      "opcode": "1000004A",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsubfp [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubfp128",
      "description": "Vector128 Subtract Floating Point",
      "opcode": "14000050",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsubfp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubsbs",
      "description": "Vector Subtract Signed Byte Saturate",
      "opcode": "10000700",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsubsbs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubshs",
      "description": "Vector Subtract Signed Half Word Saturate",
      "opcode": "10000740",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsubshs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubsws",
      "description": "Vector Subtract Signed Word Saturate",
      "opcode": "10000780",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsubsws [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsububm",
      "description": "Vector Subtract Unsigned Byte Modulo",
      "opcode": "10000400",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsububm [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsububs",
      "description": "Vector Subtract Unsigned Byte Saturate",
      "opcode": "10000600",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsububs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubuhm",
      "description": "Vector Subtract Unsigned Half Word Modulo",
      "opcode": "10000440",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsubuhm [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubuhs",
      "description": "Vector Subtract Unsigned Half Word Saturate",
      "opcode": "10000640",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsubuhs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubuwm",
      "description": "Vector Subtract Unsigned Word Modulo",
      "opcode": "10000480",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vsubuwm [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsubuws",
      "description": "Vector Subtract Unsigned Word Saturate",
      "opcode": "10000680",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsubuws [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsumsws",
      "description": "Vector Sum Across Signed Word Saturate",
      "opcode": "10000788",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsumsws [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsum2sws",
      "description": "Vector Sum Across Partial (1/2) Signed Word Saturate",
      "opcode": "10000688",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsum2sws [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsum4sbs",
      "description": "Vector Sum Across Partial (1/4) Signed Byte Saturate",
      "opcode": "10000708",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsum4sbs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsum4shs",
      "description": "Vector Sum Across Partial (1/4) Signed Half Word Saturate",
      "opcode": "10000648",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsum4shs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vsum4ubs",
      "description": "Vector Sum Across Partial (1/4) Unsigned Byte Saturate",
      "opcode": "10000608",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vsum4ubs [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vupkhpx",
      "description": "Vector Unpack High Pixel",
      "opcode": "1000034E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupkhpx [VD], [VB]"
    },
    {
      "mnemonic": "vupkhsb",
      "description": "Vector Unpack High Signed Byte",
      "opcode": "1000020E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupkhsb [VD], [VB]"
    },
    {
      "mnemonic": "vupkhsb128",
      "description": "Vector128 Unpack High Signed Byte",
      "opcode": "18000380",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupkhsb128 [VD], [VB]"
    },
    {
      "mnemonic": "vupkhsh",
      "description": "Vector Unpack High Signed Half Word",
      "opcode": "1000024E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupkhsh [VD], [VB]"
    },
    {
      "mnemonic": "vupklpx",
      "description": "Vector Unpack Low Pixel",
      "opcode": "100003CE",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupklpx [VD], [VB]"
    },
    {
      "mnemonic": "vupklsb",
      "description": "Vector Unpack Low Signed Byte",
      "opcode": "1000028E",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupklsb [VD], [VB]"
    },
    {
      "mnemonic": "vupklsb128",
      "description": "Vector128 Unpack Low Signed Byte",
      "opcode": "180003C0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupklsb128 [VD], [VB]"
    },
    {
      "mnemonic": "vupklsh",
      "description": "Vector Unpack Low Signed Half Word",
      "opcode": "100002CE",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vupklsh [VD], [VB]"
    },
    {
      "mnemonic": "vxor",
      "description": "Vector Logical XOR",
      "opcode": "100004C4",
      "form": "VX",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "AltiVec"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vxor [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vxor128",
      "description": "Vector128 Logical XOR",
      "opcode": "14000310",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vxor128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmulfp128",
      "description": "Vector128 Multiply Floating-Point",
      "opcode": "14000090",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmulfp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmaddcfp128",
      "description": "Vector128 Multiply Add Floating Point",
      "opcode": "14000110",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmaddcfp128 [VD], [VA], [VD], [VB]"
    },
    {
      "mnemonic": "vmsum3fp128",
      "description": "Vector128 Multiply Sum 3-way Floating Point",
      "opcode": "14000190",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmsum3fp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vmsum4fp128",
      "description": "Vector128 Multiply Sum 4-way Floating-Point",
      "opcode": "140001D0",
      "form": "VX128",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VA",
          "conditional": false
        },
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vmsum4fp128 [VD], [VA], [VB]"
    },
    {
      "mnemonic": "vpermwi128",
      "description": "Vector128 Permutate Word Immediate",
      "opcode": "18000210",
      "form": "VX128_P",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vpermwi128 [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vcfpsxws128",
      "description": "Vector128 Convert From Floating-Point to Signed Fixed-Point Word Saturate",
      "opcode": "18000230",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vcfpsxws128 [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vcfpuxws128",
      "description": "Vector128 Convert From Floating-Point to Unsigned Fixed-Point Word Saturate",
      "opcode": "18000270",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        },
        {
          "field": "VSCR",
          "conditional": false
        }
      ],
      "disassembly": "vcfpuxws128 [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vcsxwfp128",
      "description": "Vector128 Convert From Signed Fixed-Point Word to Floating-Point",
      "opcode": "180002B0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vcsxwfp128 [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vcuxwfp128",
      "description": "Vector128 Convert From Unsigned Fixed-Point Word to Floating-Point",
      "opcode": "180002F0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        },
        {
          "field": "UIMM",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vcuxwfp128 [VD], [VB], [UIMM]"
    },
    {
      "mnemonic": "vpkd3d128",
      "description": "Vector128 Pack D3Dtype, Rotate Left Immediate and Mask Insert",
      "opcode": "18000610",
      "form": "VX128_4",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": ""
    },
    {
      "mnemonic": "vrlimi128",
      "description": "Vector128 Rotate Left Immediate and Mask Insert",
      "opcode": "18000710",
      "form": "VX128_4",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": "vrlimi128 [VD], [VB], [IMM], [z]"
    },
    {
      "mnemonic": "vupkd3d128",
      "description": "Vector128 Unpack D3Dtype",
      "opcode": "180007F0",
      "form": "VX128_3",
      "group": "v",
      "category": "Vector / VMX (AltiVec)",
      "tags": [
        "VMX128",
        "Xbox 360 Extension"
      ],
      "source_file": "src/xenia/cpu/ppc/ppc_emit_altivec.cc",
      "inputs": [
        {
          "field": "VB",
          "conditional": false
        }
      ],
      "outputs": [
        {
          "field": "VD",
          "conditional": false
        }
      ],
      "disassembly": ""
    }
  ]
}