# `negx` — Negate

> **Category:** [Integer ALU](../categories/alu.md) · **Form:** [XO](../forms/XO.md) · **Opcode:** `0x7c0000d0`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `neg` | `negx` | — | Negate |
| `nego` | `negx` | OE=1 | Negate |
| `neg.` | `negx` | Rc=1 | Negate |
| `nego.` | `negx` | OE=1, Rc=1 | Negate |

## Syntax

```asm
neg[OE][Rc] [RD], [RA]
```

## Encoding

### `negx` — form `XO`

- **Opcode word:** `0x7c0000d0`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `104`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `RT` | destination GPR |
| 11–15 | `RA` | source A |
| 16–20 | `RB` | source B |
| 21 | `OE` | overflow-enable flag |
| 22–30 | `XO` | extended opcode (9 bits) |
| 31 | `Rc` | record-form flag |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RA` | negx: read | Source GPR (`r0`–`r31`). |
| `RD` | negx: write | Destination GPR. |
| `CR` | negx: write (conditional) | Condition-register update. When `Rc=1`, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result. |
| `OE` | negx: write (conditional) | Overflow-enable bit. When 1, the instruction updates `XER[OV]` and stickies `XER[SO]` on signed overflow. |

## Register Effects

### `negx`

- **Reads (always):** `RA`
- **Reads (conditional):** _none_
- **Writes (always):** `RD`
- **Writes (conditional):** `CR`, `OE`

## Status-Register Effects

- `negx`: **CR0** ← signed-compare(result, 0) with `SO ← XER[SO]`, when `Rc=1`.; **XER[OV]** ← signed-overflow(result); **XER[SO]** stickies, when `OE=1`.

## Operation (pseudocode)

```
RT <- ~(RA) + 1
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`negx`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="negx"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_alu.cc:406`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_alu.cc#L406)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:197`](../../../crates/sylpheed-ppc/src/opcode.rs#L197)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:981`](../../../crates/sylpheed-ppc/src/decoder.rs#L981)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_negx(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- ¬(RA) + 1
  if (i.XO.OE) {
    // Stub implementation.
    // TODO: Handle overflow flag for XER.
    // NOTE: 535507D4 (Raiden Fighters Aces) never seems to rely on this
    //   behavior, despite having OE set.
    Value* v = f.LoadGPR(i.XO.RA);
    if (v->AsUint64() == 0x8000000000000000) {
      f.StoreGPR(i.XO.RT, v);
      return 0;
    }
  }
  Value* v = f.Neg(f.LoadGPR(i.XO.RA));
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **Two's-complement negate.** `RT ← ~RA + 1`, equivalent to `0 − RA`. A specialisation of [`subfx`](subfx.md) where `RB` is implicit zero.
- **`INT64_MIN` is its own negation.** `neg(0x8000000000000000) = 0x8000000000000000` — the only fixed point. `nego` should set `XER[OV]` in this case (it is the canonical signed-overflow trigger), but **xenia-rs does not implement `OE`** ([`interpreter.rs:201`](https://git.mc02.dev/fabi/xenia-rs/src/commit/8401d4d5112849bf7b0f78f9d620f3620b1ce58d/crates/xenia-cpu/src/interpreter.rs) has no `oe()` branch).
- **`RB` field unused.** Set to 0 by assemblers; ignored.
- **`Rc=1` CR0 update truncates to 32 bits in xenia-rs.** [`interpreter.rs:204`](https://git.mc02.dev/fabi/xenia-rs/src/commit/8401d4d5112849bf7b0f78f9d620f3620b1ce58d/crates/xenia-cpu/src/interpreter.rs). Important: `neg.` of a 64-bit value with high bits set will give a CR0 that doesn't match spec (which compares the full 64-bit `~RA + 1` to zero).
- **No carry produced.** Use [`subfic`](subficx.md) `RT, RA, 0` (`RT ← 0 − RA` with carry) when you need the borrow.
- **Latency: single cycle.** Negate is the cheapest XO-form ALU operation (cheaper than `subf` despite being a special case, because there's no `RB` operand fetch).

## Related Instructions

- [`subfx`](subfx.md) — generalisation: `neg RT, RA` ≡ `subf RT, RA, 0` (but the latter requires materialising 0 in a register).
- [`subfic`](subficx.md) — `RT ← SIMM − RA` with `XER[CA]`; `subfic RT, RA, 0` produces a borrow.
- [`addx`](addx.md), [`addmex`](addmex.md), [`addzex`](addzex.md) — for chained negation (multi-word two's complement).
- `not` (simplified) — bit-wise complement via `nor RA, RS, RS`; distinct from negate.

## IBM Reference

- [AIX 7.3 — `neg` (Negate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-neg-negate-instruction)