# `mtcrf` — Move to Condition Register Fields

> **Category:** [Control / CR / SPR](../categories/control.md) · **Form:** [XFX](../forms/XFX.md) · **Opcode:** `0x7c000120`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `mtcrf` | `mtcrf` | — | Move to Condition Register Fields |

## Syntax

```asm
mtcrf [CRM], [RS]
```

## Encoding

### `mtcrf` — form `XFX`

- **Opcode word:** `0x7c000120`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `144`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (31) |
| 6–10 | `RT` | destination / source GPR |
| 11–20 | `spr/tbr/FXM` | SPR/TBR number (byte-swapped halves) or CR field mask |
| 21–30 | `XO` | extended opcode |
| 31 | `—` | reserved |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `RS` | mtcrf: read | Source GPR (alias for RD in some stores). |
| `CRM` | mtcrf: write | 8-bit CR field mask used by `mtcrf` — one bit per CR field. |

## Register Effects

### `mtcrf`

- **Reads (always):** `RS`
- **Reads (conditional):** _none_
- **Writes (always):** `CRM`
- **Writes (conditional):** _none_

## Status-Register Effects

_No condition-register or status-register effects._

## Operation (pseudocode)

```
for i in 0..7:
    if CRM[i] then CR[i] <- (RS)[32+i*4 : 35+i*4]
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`mtcrf`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="mtcrf"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_control.cc:734`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_control.cc#L734)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:178`](../../../crates/sylpheed-ppc/src/opcode.rs#L178)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:894`](../../../crates/sylpheed-ppc/src/decoder.rs#L894)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_mtcrf(PPCHIRBuilder& f, const InstrData& i) {
  // mtocrf FXM,RS
  // count <- 0
  // do i = 0 to 7
  //   if FXMi = 1 then
  //     n <- i
  //     count <- count + 1
  // if count = 1 then
  //   CR4un + 32 : 4un + 35 <- RS4un + 32:4un + 35

  Value* v = f.LoadGPR(i.XFX.RT);
  if (i.XFX.spr & (1 << 9)) {
    uint32_t bits = (i.XFX.spr & 0x1FF) >> 1;
    int count = 0;
    int cri = 0;
    for (int b = 0; b <= 7; ++b) {
      if (bits & (1 << b)) {
        cri = 7 - b;
        ++count;
      }
    }
    if (count == 1) {
      f.StoreCR(cri, v);
    } else {
      // Invalid; store zero to CR.
      f.StoreCR(f.LoadZeroInt64());
    }
  } else {
    uint32_t bits = (i.XFX.spr & 0x1FF) >> 1;
    for (int b = 0; b <= 7; ++b) {
      if (bits & (1 << b)) {
        int cri = 7 - b;
        f.StoreCR(cri, v);
      }
    }
  }
  return 0;
}
```
</details>

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## Special Cases & Edge Conditions

- **`CRM` is an 8-bit field-mask, MSB-first.** Each bit of `CRM` corresponds to one CR field: `CRM[0]` (mask bit `0x80`) selects CR0, `CRM[1]` (`0x40`) selects CR1, …, `CRM[7]` (`0x01`) selects CR7. Each *set* mask bit causes the corresponding 4-bit slice of `RS[32:63]` to overwrite that CR field; clear mask bits leave the field untouched.
- **Slice positions inside `RS`.** Big-endian: bits 32..35 of `RS` map to CR0, bits 36..39 to CR1, …, bits 60..63 to CR7. The high 32 bits of `RS` are ignored.
- **`mtcr RS` simplified mnemonic.** When `CRM = 0xFF`, all eight CR fields are written; assemblers fold this into `mtcr RS`. This is the dominant form (function epilogue restoring the saved CR).
- **`mtocrf` variant.** PowerISA defines `mtocrf` as the single-field variant — encoded with the high bit of FXM set and exactly one CRM bit set. xenia-rs treats both as the same opcode and processes whatever `CRM` mask is present, so `mtocrf` works correctly without special handling.
- **Use case in ABI.** Save/restore non-volatile CR fields (CR2, CR3, CR4 on the Xbox 360 ABI). The standard restore is `lwz r12, 8(r1); mtcrf 0x38, r12` — `0x38` = bits for CR2|CR3|CR4 — preserving the volatile fields the callee may have already updated.
- **No CR0 / XER side effects.** `mtcrf` does not record into CR0; XER is untouched.
- **xenia exact match.** xenia-rs decomposes the CR into a `u32`, applies a per-field mask, and reassembles via `set_cr`. The 8-bit `CRM` walk matches the spec exactly.
- **Not synchronising.** Reorderable.

## Related Instructions

- [`mfcr`](mfcr.md) — read the entire CR into a GPR.
- [`mcrf`](mcrf.md) — copy one CR field to another (no GPR involved).
- [`mcrxr`](mcrxr.md), [`mcrfs`](mcrfs.md) — narrower CR-field moves from XER / FPSCR.
- [`crand`](crand.md), [`cror`](cror.md), … — bit-level CR manipulation.

### Simplified Mnemonics

| Simplified | Expansion           | Notes |
| ---        | ---                 | --- |
| `mtcr RS`  | `mtcrf 0xFF, RS`    | write all eight CR fields from low half of RS |

`mtocrf RS, FXM` is a related encoding handled by the same xenia-rs slot.

## IBM Reference

- [AIX 7.3 — `mtcrf` (Move to Condition Register Fields)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-mtcrf-move-condition-register-fields-instruction)
- [AIX 7.3 — Condition register simplified mnemonics](https://www.ibm.com/docs/en/aix/7.3.0?topic=mnemonics-condition-register-logical-simplified)