# `stw` — Store Word
> **Category:** [Memory](../categories/memory.md) · **Form:** [D](../forms/D.md) · **Opcode:** `0x90000000`
## Assembler Mnemonics
| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `stw` | `stw` | — | Store Word |
| `stwu` | `stwu` | — | Store Word with Update |
| `stwux` | `stwux` | — | Store Word with Update Indexed |
| `stwx` | `stwx` | — | Store Word Indexed |
## Syntax
```asm
stw [RS], [d]([RA0])
stwu [RS], [d]([RA])
stwux [RS], [RA], [RB]
stwx [RS], [RA0], [RB]
```
## Encoding
### `stw` — form `D`
- **Opcode word:** `0x90000000`
- **Primary opcode (bits 0–5):** `36`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
### `stwu` — form `D`
- **Opcode word:** `0x94000000`
- **Primary opcode (bits 0–5):** `37`
- **Extended opcode:** —
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT` | destination GPR (or RS when storing) |
| 11–15 | `RA` | source GPR (0 ⇒ literal 0 for RA0 forms) |
| 16–31 | `D/SI/UI` | 16-bit signed or unsigned immediate |
### `stwux` — form `X`
- **Opcode word:** `0x7c00016e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `183`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
### `stwx` — form `X`
- **Opcode word:** `0x7c00012e`
- **Primary opcode (bits 0–5):** `31`
- **Extended opcode:** `151`
- **Synchronising:** no
| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode |
| 6–10 | `RT/FRT/VRT` | destination |
| 11–15 | `RA/FRA/VRA` | source A |
| 16–20 | `RB/FRB/VRB` | source B |
| 21–30 | `XO` | extended opcode (10 bits) |
| 31 | `Rc` | record-form flag |
## Operands
| Field | Role | Description |
| --- | --- | --- |
| `RS` | stw: read; stwu: read; stwux: read; stwx: read | Source GPR (alias for RD in some stores). |
| `RA0` | stw: read; stwx: read | Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, **not** `r0`. |
| `d` | stw: read; stwu: read | 16-bit signed displacement (`d`) added to the base address register. |
| `RA` | stwu: read; stwu: write; stwux: read; stwux: write | Source GPR (`r0`–`r31`). |
| `RB` | stwux: read; stwx: read | Source GPR. |
## Register Effects
### `stw`
- **Reads (always):** `RS`, `RA0`, `d`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
### `stwu`
- **Reads (always):** `RS`, `RA`, `d`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_
### `stwux`
- **Reads (always):** `RS`, `RA`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** `RA`
- **Writes (conditional):** _none_
### `stwx`
- **Reads (always):** `RS`, `RA0`, `RB`
- **Reads (conditional):** _none_
- **Writes (always):** _none_
- **Writes (conditional):** _none_
## Status-Register Effects
_No condition-register or status-register effects._
## Operation (pseudocode)
```
EA <- (RA|0) + EXTS(d)
MEM(EA, 4) <- (RS)[32:63]
```
## C Translation Example
```c
/* stw RS, d(RA) */
uint64_t base = (insn.RA == 0) ? 0 : r[insn.RA];
uint32_t ea = (uint32_t)(base + (int64_t)(int16_t)insn.D);
mem_write_u32_be(ea, (uint32_t)r[insn.RS]);
```
## Implementation References
**`stw`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="stw"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_memory.cc:507`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_memory.cc#L507)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:274`](../../../crates/sylpheed-ppc/src/opcode.rs#L274)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:474`](../../../crates/sylpheed-ppc/src/decoder.rs#L474)
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stw(PPCHIRBuilder& f, const InstrData& i) {
// if RA = 0 then
// b <- 0
// else
// b <- (RA)
// EA <- b + EXTS(D)
// MEM(EA, 4) <- (RS)[32:63]
Value* b;
if (i.D.RA == 0) {
b = f.LoadZeroInt64();
} else {
b = f.LoadGPR(i.D.RA);
}
Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS));
f.StoreOffset(b, offset,
f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT32_TYPE)));
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stwu(PPCHIRBuilder& f, const InstrData& i) {
// EA <- (RA) + EXTS(D)
// MEM(EA, 4) <- (RS)[32:63]
// RA <- EA
Value* ea = CalculateEA_i(f, i.D.RA, XEEXTS16(i.D.DS));
f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.D.RT), INT32_TYPE)));
StoreEA(f, i.D.RA, ea);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stwux(PPCHIRBuilder& f, const InstrData& i) {
// EA <- (RA) + (RB)
// MEM(EA, 4) <- (RS)[32:63]
// RA <- EA
Value* ea = CalculateEA(f, i.X.RA, i.X.RB);
f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE)));
StoreEA(f, i.X.RA, ea);
return 0;
}
```
Canary emitter (frozen snapshot @ f21ebd49e9)
```cpp
int InstrEmit_stwx(PPCHIRBuilder& f, const InstrData& i) {
// if RA = 0 then
// b <- 0
// else
// b <- (RA)
// EA <- b + (RB)
// MEM(EA, 4) <- (RS)[32:63]
Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
f.Store(ea, f.ByteSwap(f.Truncate(f.LoadGPR(i.X.RT), INT32_TYPE)));
return 0;
}
```