# `vmsumuhs` — Vector Multiply-Sum Unsigned Half Word Saturate

> **Category:** [VMX (Altivec)](../categories/vmx.md) · **Form:** [VA](../forms/VA.md) · **Opcode:** `0x10000027`

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## Assembler Mnemonics

| Mnemonic | XML entry | Flags | Description |
| --- | --- | --- | --- |
| `vmsumuhs` | `vmsumuhs` | — | Vector Multiply-Sum Unsigned Half Word Saturate |

## Syntax

```asm
vmsumuhs [VD], [VA], [VB], [VC]
```

## Encoding

### `vmsumuhs` — form `VA`

- **Opcode word:** `0x10000027`
- **Primary opcode (bits 0–5):** `4`
- **Extended opcode:** `39`
- **Synchronising:** no

| Bits | Field | Meaning |
| --- | --- | --- |
| 0–5 | `OPCD` | primary opcode (4) |
| 6–10 | `VRT` | destination vector register |
| 11–15 | `VRA` | source A |
| 16–20 | `VRB` | source B |
| 21–25 | `VRC` | source C / shift |
| 26–31 | `XO` | extended opcode (6 bits) |

## Operands

| Field | Role | Description |
| --- | --- | --- |
| `VA` | vmsumuhs: read | Source A vector register. |
| `VB` | vmsumuhs: read | Source B vector register. |
| `VC` | vmsumuhs: read | Source C vector register / 3-bit selector. |
| `VD` | vmsumuhs: write | Destination vector register. |
| `VSCR` | vmsumuhs: write | Vector Status and Control Register (NJ/SAT bits). |

## Register Effects

### `vmsumuhs`

- **Reads (always):** `VA`, `VB`, `VC`
- **Reads (conditional):** _none_
- **Writes (always):** `VD`, `VSCR`
- **Writes (conditional):** _none_

## Status-Register Effects

- `vmsumuhs`: **VSCR[SAT]** may be stickied on saturating vector operations.

## Operation (pseudocode)

```
; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.
```

## C Translation Example

```c
/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */
```

## Implementation References

**`vmsumuhs`**
- Canary XML: [`tools/ppc-instructions.xml` — search for `mnem="vmsumuhs"`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/tools/ppc-instructions.xml)
- Canary emitter: [`src/xenia/cpu/ppc/ppc_emit_altivec.cc:1049`](https://github.com/xenia-canary/xenia-canary/blob/f21ebd49e979e44f081f474df78c3fbfee9cb3f2/src/xenia/cpu/ppc/ppc_emit_altivec.cc#L1049)
- Sylpheed opcode: [`crates/sylpheed-ppc/src/opcode.rs:384`](../../../crates/sylpheed-ppc/src/opcode.rs#L384)
- Sylpheed decoder: [`crates/sylpheed-ppc/src/decoder.rs:697`](../../../crates/sylpheed-ppc/src/decoder.rs#L697)
<details><summary>Canary emitter (frozen snapshot @ <code>f21ebd49e9</code>)</summary>

```cpp
int InstrEmit_vmsumuhs(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}
```
</details>

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## Special Cases & Edge Conditions

- **Unsigned half-word multiply-sum, saturating.** Per word lane:
  ```
  VD[i] = clamp(VC[i] + uint16(VA[2*i]) * uint16(VB[2*i])
                     + uint16(VA[2*i+1]) * uint16(VB[2*i+1]), 0, UINT32_MAX)
  ```
  Two unsigned-half × unsigned-half products plus an unsigned-word accumulator, clamped to `uint32`.
- **Wide-then-clamp ordering.** The IBM specification accumulates into a wide sum and clamps only the *final* result to `u32`. ⚠️ Canary does not implement `vmsumuhs`: its emitter is `XEINSTRNOTIMPLEMENTED`, so translating one logs "Unimplemented instr" and, with the default `break_on_unimplemented_instructions`, breaks.
- **`VSCR[SAT]` is sticky-set** if any lane clamps. Only the upper bound `0xFFFF_FFFF` ever triggers; unsigned overflow on the low side is impossible.
- **Big-endian half lanes.** Lane 0 is the most-significant half.
- **No XER, no exceptions.**
- **Aliasing legal.**
- **No VMX128 sibling.**
- **Common usage.** Per-pixel summed-area calculations with overflow detection; high-precision unsigned-half FIR convolution.

## Related Instructions

- [`vmsumuhm`](vmsumuhm.md) — same shape, modulo (no clamp, no SAT flag).
- [`vmsumshs`](vmsumshs.md) — signed half multiply-sum, saturating.
- [`vmsumubm`](vmsumubm.md), [`vmsummbm`](vmsummbm.md) — multiply-sum at byte width.
- [`vadduws`](vadduws.md) — unsigned saturating word add for further accumulation.
- [`mtvscr`](../control/mtvscr.md) / [`mfvscr`](../control/mfvscr.md) — read or clear `VSCR[SAT]`.

## IBM Reference

- [AIX 7.3 — `vmsumuhs` (Vector Multiply-Sum Unsigned Half Word Saturate)](https://www.ibm.com/docs/en/aix/7.3.0?topic=set-vmsumuhs-vector-multiply-sum-unsigned-half-word-saturate-instruction)
- [IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Multiply-Sum Family](https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf)