Sylpheed/tools/ppc-manual/control/mfvscr.md

mfvscr — Move from VSCR

Category: Control / CR / SPR · Form: VX · Opcode: 0x10000604

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mfvscr	mfvscr	—	Move from VSCR

Syntax

(no disassembly template)

Encoding

mfvscr — form VX

• Opcode word: 0x10000604
• Primary opcode (bits 0–5): 4
• Extended opcode: 1540
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VSCR	mfvscr: read	Vector Status and Control Register (NJ/SAT bits).
VD	mfvscr: write	Destination vector register.

Register Effects

mfvscr

• Reads (always): VSCR
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mfvscr

• Canary XML: tools/ppc-instructions.xml — search for mnem="mfvscr"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:303
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:176
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:654

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mfvscr(PPCHIRBuilder& f, const InstrData& i) {
  // mfvscr VD - Move from VSCR to VD
  f.StoreVR(i.VX.VD,
            f.LoadContext(offsetof(PPCContext, vscr_vec), VEC128_TYPE));
  return 0;
}

Special Cases & Edge Conditions

• Operation. Reads the 32-bit Vector Status and Control Register (VSCR) into the low 32 bits of the rightmost word of VD (the 128-bit vector register). The other 96 bits of VD are zeroed. PowerISA places the result at byte offset 12..15 (big-endian within the 128-bit register).

• VSCR contents (Xenon-relevant).

  Bit	Name	Meaning
  16	NJ	Non-Java mode (denormal handling for IEEE-754 single-prec vector ops)
  31	SAT	Saturation — sticky; set whenever a saturating vector op clamps

  All other bits are reserved (zero).

• SAT is sticky. Once a saturating vector instruction clamps a result, VSCR[SAT] becomes 1 and stays 1 until explicitly cleared via mtvscr. Software polls it after a vector batch to detect overflow.

• NJ controls denormals. When NJ=1 (the Xenon's default), AltiVec single-precision ops flush denormal inputs/outputs to zero (non-IEEE behaviour); NJ=0 enforces full IEEE.

• VRSAVE. Writing the entire 128-bit VD consumes a vector register slot; software wishing to honour VRSAVE bookkeeping should ensure the chosen VD is in the live mask.

• Canary simplification. mfvscr copies Canary's vscr_vec into VD. Only mtvscr writes that value (it starts with NJ set), so SAT never appears: Canary does not record saturation at all.

• Not synchronising.

Related Instructions

• mtvscr — write VSCR from a vector register (the inverse).
• mfspr — for non-vector status registers; VSCR has its own opcode.
• AltiVec saturating-arithmetic ops (e.g., vaddubs, vsubuhs) — primary writers of VSCR[SAT].

mfvscr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mfvscr (Move from VSCR)
• PowerISA v2.07B, Book I §6.6 — VSCR layout and the SAT / NJ definitions.