Sylpheed/tools/ppc-manual/memory/lvlxl.md

lvlxl — Load Vector Left Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c00060e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lvlxl	lvlxl	—	Load Vector Left Indexed LRU
lvlxl128	lvlxl128	—	Load Vector Left Indexed LRU 128

Syntax

lvlxl [VD], [RA0], [RB]
lvlxl128 [VD], [RA0], [RB]

Encoding

lvlxl — form X

• Opcode word: 0x7c00060e
• Primary opcode (bits 0–5): 31
• Extended opcode: 775
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

lvlxl128 — form VX128_1

• Opcode word: 0x10000603
• Primary opcode (bits 0–5): 4
• Extended opcode: 1539
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
RA0	lvlxl: read; lvlxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	lvlxl: read; lvlxl128: read	Source GPR.
VD	lvlxl: write; lvlxl128: write	Destination vector register.

Register Effects

lvlxl

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

lvlxl128

• Reads (always): RA0, RB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lvlxl

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvlxl"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:222
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:142
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:953

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvlxl(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvlx(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:216) ──
int InstrEmit_lvlx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvlx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* val = f.LoadVectorLeft(ea);
  f.StoreVR(vd, val);
  return 0;
}

lvlxl128

• Canary XML: tools/ppc-instructions.xml — search for mnem="lvlxl128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:225
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:143
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:539

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lvlxl128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvlx128(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:219) ──
int InstrEmit_lvlx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_lvlx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:208) ──
int InstrEmit_lvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                    uint32_t ra, uint32_t rb) {
  Value* ea = CalculateEA_0(f, ra, rb);

  Value* val = f.LoadVectorLeft(ea);
  f.StoreVR(vd, val);
  return 0;
}

Special Cases & Edge Conditions

• Same data effect as lvlx, with LRU cache hint. Reads (16 - (EA mod 16)) bytes starting at EA into the left side of VD; right side zero-filled. The l suffix tells the cache the line is least-recently-used — likely streaming, evict early under pressure.
• Hint ignored under emulation. Canary's lvlxl simply calls its lvlx emitter. Functional behaviour is identical to lvlx.
• No alignment masking. Like lvlx, the exact EA controls how data shifts into the vector.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of the VMX128 / Cell BE extended set, not in baseline Altivec.
• Used in single-pass streaming reads. Decoder loops that consume each vector once benefit from the LRU hint on real hardware; Canary gains nothing from it.
• VMX128 sibling (lvlxl128). Identical semantics; alternative operand encoding addressing v0..v127.

Related Instructions

• lvlx, lvlx128 — non-hint load-left variants.
• lvrx, lvrxl — load-right partner.
• stvlxl, stvrxl — symmetric stores.
• lvx, lvxl — aligned vector load family.

IBM Reference

• AIX 7.3 — lvlxl (Load Vector Left Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for VMX128 cache-hint deltas.