Sylpheed/tools/ppc-manual/memory/stdbrx.md

stdbrx — Store Doubleword Byte-Reverse Indexed

Category: Memory · Form: X · Opcode: 0x7c000528

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stdbrx	stdbrx	—	Store Doubleword Byte-Reverse Indexed

Syntax

stdbrx [RS], [RA0], [RB]

Encoding

stdbrx — form X

• Opcode word: 0x7c000528
• Primary opcode (bits 0–5): 31
• Extended opcode: 660
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RS	stdbrx: read	Source GPR (alias for RD in some stores).
RA0	stdbrx: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stdbrx: read	Source GPR.

Register Effects

stdbrx

• Reads (always): RS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stdbrx

• Canary XML: tools/ppc-instructions.xml — search for mnem="stdbrx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:691
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:231
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:944

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stdbrx(PPCHIRBuilder& f, const InstrData& i) {
  // if RA = 0 then
  //   b <- 0
  // else
  //   b <- (RA)
  // EA <- b + (RB)
  // MEM(EA, 8) <- bswap(RS)
  Value* ea = CalculateEA_0(f, i.X.RA, i.X.RB);
  f.Store(ea, f.LoadGPR(i.X.RT));
  return 0;
}

Special Cases & Edge Conditions

• Writes little-endian doubleword. Reverses the 8 bytes of RS and stores them at EA. Compared to a regular std, the byte at EA becomes RS[56:63] (least-significant), and the byte at EA+7 becomes RS[0:7] (most-significant). Canary stores RS without the byte swap std applies, which on its little-endian host writes the bytes reversed.
• Used to emit little-endian payloads. Symmetric counterpart of ldbrx. Common when writing PC-side file formats, network packets, or PE/COFF headers from PowerPC code.
• X-form only — no update form, no DS-form. Only the indexed form exists. EA = (RA|0) + RB. Pointer-bumping requires a separate addi.
• RA0 semantics. When RA = 0, base is literal zero. stdbrx RS, 0, RB writes at exact RB.
• Alignment. Hardware tolerates unaligned 8-byte writes. Cache-inhibited storage may raise alignment exceptions on real hardware.
• No CR / FPSCR effects. Pure data movement.
• Cache-line straddling cost. As with std, writes that cross a 128-byte line boundary touch two cache lines; keep doublewords 8-byte aligned for best performance.

Related Instructions

• ldbrx — load doubleword byte-reverse (the matching load).
• stwbrx, sthbrx — narrower byte-reverse stores.
• std, stdx — non-reversing doubleword stores.

IBM Reference

• AIX 7.3 — stdbrx (Store Doubleword Byte-Reverse Indexed)
• PowerISA v2.07B Book II § "Byte-Reverse Storage Access".