Sylpheed/tools/ppc-manual/alu/addzex.md

addzex — Add to Zero Extended

Category: Integer ALU · Form: XO · Opcode: 0x7c000194

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
addze	addzex	—	Add to Zero Extended
addzeo	addzex	OE=1	Add to Zero Extended
addze.	addzex	Rc=1	Add to Zero Extended
addzeo.	addzex	OE=1, Rc=1	Add to Zero Extended

Syntax

addze[OE][Rc] [RD], [RA]

Encoding

addzex — form XO

• Opcode word: 0x7c000194
• Primary opcode (bits 0–5): 31
• Extended opcode: 202
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	addzex: read	Source GPR (r0–r31).
CA	addzex: read; addzex: write	XER[CA] carry bit. Read by add-with-carry/subtract-with-borrow instructions, written by carrying instructions.
RD	addzex: write	Destination GPR.
OE	addzex: write (conditional)	Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.
CR	addzex: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

addzex

• Reads (always): RA, CA
• Reads (conditional): none
• Writes (always): RD, CA
• Writes (conditional): OE, CR

Status-Register Effects

• addzex: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.; XER[CA] ← carry-out of the add / borrow-in of the subtract (always).

Operation (pseudocode)

RT <- (RA) + CA
CA <- carry_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

addzex

• Canary XML: tools/ppc-instructions.xml — search for mnem="addzex"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:172
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:16
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:985

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_addzex(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- (RA) + CA
  // CA <- carry bit
  Value* ra = f.LoadGPR(i.XO.RA);
  Value* v = f.AddWithCarry(ra, f.LoadZeroInt64(), f.LoadCA());
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    // With XER[SO] update too.
    // e.update_xer_with_overflow_and_carry(b.CreateExtractValue(v, 1));
    XEINSTRNOTIMPLEMENTED();
  } else {
    // Just CA update.
    f.StoreCA(AddWithCarryDidCarry(f, ra, f.LoadZeroInt64(), f.LoadCA()));
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• No RB field used. Like addmex, this XO-form instruction ignores the RB slot. Assemblers emit zero there.
• Operation is RA + 0 + CA ≡ RA + CA. Used to terminate the high word of a multi-word add chain seeded by addcx. After the low-word addc produces the carry, all middle words use addex, and the final word that has no register operand uses addze.
• Carry-out is the simple unsigned overflow test result < ra — same predicate as addcx. CA' = 1 only if RA == ~0 && CA == 1.
• OE=1 not implemented in Canary. The branch is XEINSTRNOTIMPLEMENTED() and does not store CA; spec asks for the standard signed-overflow detect.
• 64-bit CR update on Xenon, 32-bit in Canary (f.UpdateCR(0, v) — see addx for context).
• Common idiom: extracting a carry as a 0/1. addze rT, 0 (or addze rT, rN where rN == 0) materialises XER[CA] into rT as a plain integer.

Related Instructions

• addmex — terminate with RA + (−1) + CA instead of +0.
• addex — middle of a multi-word add chain.
• addcx — seeds the chain.
• subfzex — subtract dual: ~RA + 0 + CA.

IBM Reference

• AIX 7.3 — addze (Add to Zero Extended)