Sylpheed/tools/ppc-manual/alu/isync.md

isync — Instruction Synchronize

Category: Integer ALU · Form: XL · Opcode: 0x4c00012c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
isync	isync	—	Instruction Synchronize

Syntax

isync

Encoding

isync — form XL

• Opcode word: 0x4c00012c
• Primary opcode (bits 0–5): 19
• Extended opcode: 150
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (19)
6–10	BT/BO	target / branch options
11–15	BA/BI	source A / CR bit to test
16–20	BB	source B
21–30	XO	extended opcode (10 bits)
31	LK	link flag

Operands

Field	Role	Description

Register Effects

isync

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

instruction-stream synchronisation — discards speculative state.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

isync

• Canary XML: tools/ppc-instructions.xml — search for mnem="isync"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:759
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:99
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:829

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_isync(PPCHIRBuilder& f, const InstrData& i) {
  // XEINSTRNOTIMPLEMENTED();
  f.Nop();
  return 0;
}

Special Cases & Edge Conditions

• Instruction-fetch barrier. Discards any speculatively fetched/decoded instructions and forces all subsequent ones to be re-fetched after preceding instructions complete. Required after self-modifying code, JIT-emitted code, and after MMU/page-table changes.
• Stronger than sync for instruction stream, weaker for memory stream — isync does not order stores against later loads. It only forces a fetch refresh.
• Common idiom: dcbf / icbi / sync / isync — flush data cache, invalidate instruction cache, drain memory, refetch — used by JITs and self-modifying loaders.
• No operands. Encoded as a fixed-form XL instruction; assemblers always emit 0x4c00012c.
• Canary emits f.Nop() for isync (its own XEINSTRNOTIMPLEMENTED() is commented out), while sync and eieio emit f.MemoryBarrier(). A sequential C translation needs no barrier behaviour: straight-line program order already serialises.
• Privilege level: user. Unlike most cache management ops, isync is unprivileged and frequently appears in userland trampolines.

Related Instructions

• sync — heavy memory barrier.
• eieio — I/O ordering for caching-inhibited storage.
• icbi, dcbf, dcbst — cache management ops (outside this page set) usually paired with isync.

IBM Reference

• AIX 7.3 — isync (Instruction Synchronize)