Sylpheed/tools/ppc-manual/alu/mulhwux.md

mulhwux — Multiply High Word Unsigned

Category: Integer ALU · Form: XO · Opcode: 0x7c000016

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mulhwu	mulhwux	—	Multiply High Word Unsigned
mulhwu.	mulhwux	Rc=1	Multiply High Word Unsigned

Syntax

mulhwu[Rc] [RD], [RA], [RB]

Encoding

mulhwux — form XO

• Opcode word: 0x7c000016
• Primary opcode (bits 0–5): 31
• Extended opcode: 11
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (31)
6–10	RT	destination GPR
11–15	RA	source A
16–20	RB	source B
21	OE	overflow-enable flag
22–30	XO	extended opcode (9 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
RA	mulhwux: read	Source GPR (r0–r31).
RB	mulhwux: read	Source GPR.
RD	mulhwux: write	Destination GPR.
CR	mulhwux: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

mulhwux

• Reads (always): RA, RB
• Reads (conditional): none
• Writes (always): RD
• Writes (conditional): CR

Status-Register Effects

• mulhwux: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

RT <- high_32_of_unsigned_multiply((RA)[32:63], (RB)[32:63]) zero-extended to 64

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mulhwux

• Canary XML: tools/ppc-instructions.xml — search for mnem="mulhwux"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:347
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:190
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:977

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mulhwux(PPCHIRBuilder& f, const InstrData& i) {
  // RT[32:64] <- ((RA)[32:63] × (RB)[32:63])[0:31]
  if (i.XO.OE) {
    // With XER update.
    XEINSTRNOTIMPLEMENTED();
  }

  Value* ratrunc =
      f.ZeroExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE);

  Value* rbtrunc =
      f.ZeroExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE);

  Value* v = f.Shr(f.Mul(ratrunc, rbtrunc, ARITHMETIC_UNSIGNED), 32);
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• Inputs are the low 32 bits, zero-extended. RA[32:63] and RB[32:63] are treated as unsigned, widened to 64 bits and multiplied; the high 32 bits of the product land in RT[32:63]. Canary shifts the product logically (f.Shr(…, 32)), so RT[0:31] is zero.
• Pair with mullwx for the full 64-bit unsigned product. mullw returns the low 32 sign-extended; for unsigned use, pair mulhwu with rlwinm to mask the low half. Xbox 360 compilers commonly emit this combination.
• No OE bit. Same family rule.
• Rc=1 CR0 update. Canary's f.UpdateCR(0, v) compares the low 32 bits as signed. Since that word is the unsigned high half, CR0 reports LT for any high half ≥ 0x80000000 — a known signed/unsigned pitfall with mulhwu..
• Common idiom for multi-precision arithmetic. mulhwu + mullw + addc chains build extended-precision multiplies entirely in 32-bit ops; useful for cryptographic code that targets the Xenon's 32-bit ABI.
• Multi-cycle latency like the rest of the multiply family.

Related Instructions

• mullwx — low 32 bits of the same product (sign-extended).
• mulhwx — signed high half.
• mulhdux — 64-bit unsigned high half.
• addcx, addex — used to chain 32-bit products into wider precision.

IBM Reference

• AIX 7.3 — mulhwu (Multiply High Word Unsigned)