Sylpheed/tools/ppc-manual/alu/rldimix.md

rldimix — Rotate Left Doubleword Immediate then Mask Insert

Category: Integer ALU · Form: MD · Opcode: 0x7800000c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rldimi	rldimix	—	Rotate Left Doubleword Immediate then Mask Insert
rldimi.	rldimix	Rc=1	Rotate Left Doubleword Immediate then Mask Insert

Syntax

rldimi[Rc] [RA], [RS], [SH], [MB]

Encoding

rldimix — form MD

• Opcode word: 0x7800000c
• Primary opcode (bits 0–5): 30
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (30)
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	sh	shift amount low 5 bits
21–26	mb/me	6-bit mask field (swapped halves)
27–29	XO	extended opcode
30	sh5	shift amount high bit
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rldimix: read	Source GPR (alias for RD in some stores).
SH	rldimix: read	Shift amount.
MB	rldimix: read	Mask begin bit.
RA	rldimix: write	Source GPR (r0–r31).
CR	rldimix: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rldimix

• Reads (always): RS, SH, MB
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rldimix: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rldimix

• Canary XML: tools/ppc-instructions.xml — search for mnem="rldimix"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:985
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:209
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:846

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rldimix(PPCHIRBuilder& f, const InstrData& i) {
  // n <- sh[5] || sh[0:4]
  // r <- ROTL64((RS), n)
  // b <- me[5] || me[0:4]
  // m <- MASK(b, ¬n)
  // RA <- (r & m) | ((RA)&¬m)
  uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
  uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
  uint64_t m = XEMASK(mb, ~sh);
  Value* v = f.LoadGPR(i.MD.RT);
  if (sh) {
    v = f.RotateLeft(v, f.LoadConstantInt8(sh));
  }
  if (m != 0xFFFFFFFFFFFFFFFF) {
    Value* ra = f.LoadGPR(i.MD.RA);
    v = f.Or(f.And(v, f.LoadConstantUint64(m)),
             f.And(ra, f.LoadConstantUint64(~m)));
  }
  f.StoreGPR(i.MD.RA, v);
  if (i.MD.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← (ROTL64(RS, SH) & MASK) | (RA & ~MASK). Reads the prior RA so it can preserve the bits outside the mask — this is the only rld* instruction with RA as both source and destination.
• Mask is MASK(MB, 63 − SH) — Canary's XEMASK(mb, ~sh) — the same span as rldicx, but the un-masked region is preserved from RA ((v & m) | (RA & ~m)) instead of being zeroed.
• Use to insert a bit-field. Common idiom: rldimi RA, RS, b, mask_start writes RS's low (64 - mask_start) bits into RA starting at bit b.
• SH and MB decoding is identical to the rest of the family (6-bit sh via instr.sh64(), 6-bit mb via the swap layout).
• Rc=1 CR0 update is 32-bit in Canary (f.UpdateCR(0, v)).
• No XER effect.
• Compile-time pattern. When you see rldimi r3, r4, n, m, the compiler is splicing a value into r3; recover the meaning by computing the mask MASK(m, 63 - n).

Related Instructions

• rldicx, rldiclx, rldicrx — same form family, but they zero outside the mask instead of preserving.
• rlwimix — 32-bit insert cousin.
• rldclx, rldcrx — register-shift forms (no insert variant).

IBM Reference

• AIX 7.3 — rldimi (Rotate Left Doubleword Immediate then Mask Insert)