Sylpheed/tools/ppc-manual/alu/rlwinmx.md

rlwinmx — Rotate Left Word Immediate then AND with Mask

Category: Integer ALU · Form: M · Opcode: 0x54000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
rlwinm	rlwinmx	—	Rotate Left Word Immediate then AND with Mask
rlwinm.	rlwinmx	Rc=1	Rotate Left Word Immediate then AND with Mask

Syntax

rlwinm[Rc] [RA], [RS], [SH], [MB], [ME]

Encoding

rlwinmx — form M

• Opcode word: 0x54000000
• Primary opcode (bits 0–5): 21
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RS	source GPR
11–15	RA	destination GPR
16–20	SH/RB	shift amount or source B
21–25	MB	mask begin
26–30	ME	mask end
31	Rc	record-form flag

Operands

Field	Role	Description
RS	rlwinmx: read	Source GPR (alias for RD in some stores).
SH	rlwinmx: read	Shift amount.
MB	rlwinmx: read	Mask begin bit.
ME	rlwinmx: read	Mask end bit.
RA	rlwinmx: write	Source GPR (r0–r31).
CR	rlwinmx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.

Register Effects

rlwinmx

• Reads (always): RS, SH, MB, ME
• Reads (conditional): none
• Writes (always): RA
• Writes (conditional): CR

Status-Register Effects

• rlwinmx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

rlwinmx

• Canary XML: tools/ppc-instructions.xml — search for mnem="rlwinmx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_alu.cc:1046
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:211
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:460

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_rlwinmx(PPCHIRBuilder& f, const InstrData& i) {
  // n <- SH
  // r <- ROTL32((RS)[32:63], n)
  // m <- MASK(MB+32, ME+32)
  // RA <- r & m
  Value* v = f.LoadGPR(i.M.RT);

  unsigned rotation = i.M.SH;

  uint64_t m = XEMASK(i.M.MB + 32, i.M.ME + 32);

  // in uint32 range (so no register concat/truncate/zx needed) and no rotation
  if (m < (1ULL << 32) && (rotation == 0)) {
    v = f.And(v, f.LoadConstantUint64(m));
  }
  // masks out all the bits that are rotated in from the right, so just do a
  // shift + and. the and with 0xFFFFFFFF is done instead of a truncate/zx
  // because we have a special case for it in the emitters that will just do a
  // single insn (mov reg32, lowpartofreg64), otherwise we generate
  // significantly more code from setting up the opnds of the truncate/zx
  else if (InstrCheck_rlx_only_needs_low(rotation, m)) {
    // this path is taken for like 90% of all rlwinms
    v = f.And(f.Shl(v, rotation), f.LoadConstantUint64(0xFFFFFFFF));
  }

  else {
    // (x||x)
    // cs: changed this to mask with UINT32_MAX instead of doing the
    // truncate/extend, this generates better code in the backend and is easier
    // to do analysis on
    v = f.And(v, f.LoadConstantUint64(0xFFFFFFFF));

    v = f.Or(f.Shl(v, 32), v);

    // TODO(benvanik): optimize srwi
    // TODO(benvanik): optimize slwi
    // The compiler will generate a bunch of these for the special case of SH=0.
    // Which seems to just select some bits and set cr0 for use with a branch.
    // We can detect this and do less work.
    if (i.M.SH) {
      v = f.RotateLeft(v, f.LoadConstantInt8(rotation));
    }
    // Compiler sometimes masks with 0xFFFFFFFF (identity) - avoid the work here
    // as our truncation/zero-extend does it for us.
    if (m != 0xFFFFFFFFFFFFFFFFull) {
      v = f.And(v, f.LoadConstantUint64(m));
    }
  }
  f.StoreGPR(i.M.RA, v);
  if (i.M.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

• RA ← ROTL32(RS[32:63], SH) & MASK(MB, ME). Take the low 32 bits of RS, rotate them left by SH, AND with a 32-bit mask. The high 32 bits of RA are zero (as u64 zero-extension on the result).
• The 32-bit Swiss army knife. Most 32-bit shift/extract simplified mnemonics expand to this single instruction:
  • slwi RA, RS, n ≡ rlwinm RA, RS, n, 0, 31-n — logical left shift.
  • srwi RA, RS, n ≡ rlwinm RA, RS, 32-n, n, 31 — logical right shift.
  • clrlwi RA, RS, n ≡ rlwinm RA, RS, 0, n, 31 — clear high n bits.
  • clrrwi RA, RS, n ≡ rlwinm RA, RS, 0, 0, 31-n — clear low n bits.
  • extlwi, extrwi, clrlslwi — full mnemonic family in PowerISA appendix.
• Mask convention MB..ME is contiguous when MB ≤ ME. When MB > ME, the mask is the complement of bits ME+1..MB-1 — a donut/wrap mask. Canary computes it as XEMASK(MB + 32, ME + 32) on the 64-bit word; about 90% of rlwinms take its fast path, (RS << SH) & 0xFFFFFFFF, when the mask is exactly the bits the shift keeps.
• SH is 5 bits, rotate amount 0..31.
• Rc=1 CR0 update truncates to 32 bits in Canary (f.UpdateCR(0, v)), and that does not always match spec: whenever the result's bit 32 (the low word's most-significant bit) is set, spec sees a positive 64-bit value (GT) while Canary's INT32 view is negative (LT). For a wrap mask (MB > ME) the result also has high-word bits set, as spec allows, so the two compares can disagree there too.
• No XER effect.

Related Instructions

• rlwimix — same mask family with read-modify-write insert.
• rlwnmx — register-shift version.
• rldiclx, rldicrx — 64-bit cousins.
• slwx, srwx, srawix — straight 32-bit shift instructions.
• slwi, srwi, clrlwi, clrrwi, extlwi, extrwi (simplified mnemonics).

IBM Reference

• AIX 7.3 — rlwinm (Rotate Left Word Immediate then AND with Mask)
• AIX 7.3 — Rotate / shift simplified mnemonics