Files
Sylpheed/tools/ppc-manual/alu/subfex.md
sim f3c512f2ab docs(ppc-manual): check every xenia-rs claim against Canary's source
The hand-written parts of the manual still described how the retired
xenia-rs interpreter behaved: its snapshots, Rust casts and helpers. Each of
those 490 statements is now either restated as what Canary's emitters and
x64 backend actually do (at the pinned canary_experimental commit), or
dropped where it only made sense for xenia-rs.

Checking them turned up claims that were wrong, not just outdated:

- VSCR[SAT] is never modelled in Canary (DID_SATURATE is a stub and mfvscr
  cannot see it); the pages said saturating ops set it stickily.
- Canary does not implement lswi/lswx/stswi/stswx, dcbi, mtfsb0/mtfsb1,
  vmsum*, vmhaddshs, vupkhpx/vupklpx, and most SPRs; pages described them
  as working.
- Traps evaluate TO in Canary; stvebx/stvehx/stvewx store one element, not
  16 bytes; mtmsrd writes only EE; fres/frsqrte/vrsqrtefp precision claims
  and the stfs "rounds under RN / sets FPSCR" claim contradicted the spec.
- Reservations are a 64 KiB block bitmap plus a value compare, not
  per-address tracking.

Claims that neither Canary's source nor a public spec settles are marked
unverified (NI at boot, vmaddcfp128 operand order, estimate bit-exactness).

Generated regions are untouched; re-running the generator changes nothing.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
2026-09-16 21:52:38 +02:00

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subfex — Subtract From Extended

Category: Integer ALU · Form: XO · Opcode: 0x7c000110

Assembler Mnemonics

Mnemonic XML entry Flags Description
subfe subfex Subtract From Extended
subfeo subfex OE=1 Subtract From Extended
subfe. subfex Rc=1 Subtract From Extended
subfeo. subfex OE=1, Rc=1 Subtract From Extended

Syntax

subfe[OE][Rc] [RD], [RA], [RB]

Encoding

subfex — form XO

  • Opcode word: 0x7c000110
  • Primary opcode (bits 05): 31
  • Extended opcode: 136
  • Synchronising: no
Bits Field Meaning
05 OPCD primary opcode (31)
610 RT destination GPR
1115 RA source A
1620 RB source B
21 OE overflow-enable flag
2230 XO extended opcode (9 bits)
31 Rc record-form flag

Operands

Field Role Description
RA subfex: read Source GPR (r0r31).
RB subfex: read Source GPR.
RD subfex: write Destination GPR.
CR subfex: write (conditional) Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
OE subfex: write (conditional) Overflow-enable bit. When 1, the instruction updates XER[OV] and stickies XER[SO] on signed overflow.

Register Effects

subfex

  • Reads (always): RA, RB
  • Reads (conditional): none
  • Writes (always): RD
  • Writes (conditional): CR, OE

Status-Register Effects

  • subfex: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; XER[OV] ← signed-overflow(result); XER[SO] stickies, when OE=1.

Operation (pseudocode)

RT <- ~(RA) + (RB) + CA
CA <- carry_out

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

subfex

Canary emitter (frozen snapshot @ f21ebd49e9)
int InstrEmit_subfex(PPCHIRBuilder& f, const InstrData& i) {
  // RT <- ¬(RA) + (RB) + CA
  Value* not_ra = f.Not(f.LoadGPR(i.XO.RA));
  Value* rb = f.LoadGPR(i.XO.RB);
  Value* v = f.AddWithCarry(not_ra, rb, f.LoadCA());
  f.StoreGPR(i.XO.RT, v);
  if (i.XO.OE) {
    XEINSTRNOTIMPLEMENTED();
    // e.update_xer_with_overflow_and_carry(b.CreateExtractValue(v, 1));
  } else {
    f.StoreCA(AddWithCarryDidCarry(f, not_ra, rb, f.LoadCA()));
  }
  if (i.XO.Rc) {
    f.UpdateCR(0, v);
  }
  return 0;
}

Special Cases & Edge Conditions

  • RT ← ~RA + RB + XER[CA]. The middle link of a multi-word subtract chain seeded by subfcx. XER[CA] propagates the borrow from the previous word.
  • Carry-out predicate handles the boundary case. CA' = (RB > RA) || (RB == RA && CA != 0). The second clause covers RB == RA with an incoming carry supplying the +1 — without it, the carry-out would be wrong. Canary evaluates it on the low word via AddWithCarryDidCarry(~RA, RB, CA).
  • OE=1 should set XER[OV] on signed overflow; Canary's OE branch is XEINSTRNOTIMPLEMENTED() and does not store CA.
  • 64-bit CR update on Xenon, 32-bit in Canary (f.UpdateCR(0, v)).
  • XER[CA] must be initialised (typically by subfcx). Reading stale CA is a frequent multi-word-subtract bug.
  • Symmetry with addex. subfe RT, RA, RBadde RT, ~RA, RB (with the implicit complement).
  • subfcx — seeds the chain (no CA read).
  • subfmex, subfzex — terminate the chain (~RA + 1 + CA, ~RA + 0 + CA).
  • subfx — plain subtract.
  • addex — dual.

IBM Reference