Sylpheed/tools/ppc-manual/control/mtvscr.md

mtvscr — Move to VSCR

Category: Control / CR / SPR · Form: VX · Opcode: 0x10000644

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
mtvscr	mtvscr	—	Move to VSCR

Syntax

(no disassembly template)

Encoding

mtvscr — form VX

• Opcode word: 0x10000644
• Primary opcode (bits 0–5): 4
• Extended opcode: 1604
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VB	mtvscr: read	Source B vector register.
VSCR	mtvscr: write	Vector Status and Control Register (NJ/SAT bits).

Register Effects

mtvscr

• Reads (always): VB
• Reads (conditional): none
• Writes (always): VSCR
• Writes (conditional): none

Status-Register Effects

• mtvscr: VSCR[SAT] may be stickied on saturating vector operations.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

mtvscr

• Canary XML: tools/ppc-instructions.xml — search for mnem="mtvscr"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:310
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:186
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:657

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_mtvscr(PPCHIRBuilder& f, const InstrData& i) {
  // mtvscr VB - Move from VB to VSCR
  // todo: what mtvscr does with the unused bits is implementation defined,
  // figure out what it does

  Value* v = f.LoadVR(i.VX.VB);

  Value* has_njm_value = f.Extract(v, (uint8_t)3, INT32_TYPE);

  f.SetNJM(f.IsTrue(f.And(has_njm_value, f.LoadConstantInt32(65536))));

  f.StoreContext(offsetof(PPCContext, vscr_vec), v);
  return 0;
}

Special Cases & Edge Conditions

• Operation. Reads the low 32 bits of the rightmost word of VB (bytes 12..15 in big-endian) and stores them into VSCR. Other bits of VB are ignored.
• Bits actually significant. Of the 32 source bits, only NJ (bit 16) and SAT (bit 31) are architecturally meaningful on the Xenon. All other bits should be written as zero; behaviour for non-zero values is implementation-defined.
• Clearing SAT. The dominant use is mtvscr vN with vN zeroed via vxor vN, vN, vN, which writes VSCR=0 and thereby clears the sticky SAT bit before a fresh batch of saturating vector ops.
• Setting NJ. Switching to/from "Java mode" (NJ=0, full IEEE denormal handling) versus "Non-Java mode" (NJ=1, flush-to-zero) is the other meaningful use. Game audio / DSP code occasionally toggles this to match a precise IEEE expectation.
• Canary simplification. Canary copies the source straight into its vscr_vec and sets its NJ mode from bit 16 of the low word, which switches the host's VMX MXCSR between flush-to-zero + denormals-are-zero and IEEE. SAT is not modelled: no Canary AltiVec op records it.
• Not synchronising. PowerISA does not require isync after mtvscr, but library code occasionally pairs them as a defensive measure.

Related Instructions

• mfvscr — read VSCR into a vector register (the inverse).
• AltiVec saturating ops (vaddubs, vsubuhs, …) — primary writers of VSCR[SAT]; mtvscr is the only way to clear it.
• mtspr — for non-vector control registers; VSCR has its own opcode.

mtvscr has no simplified mnemonics.

IBM Reference

• AIX 7.3 — mtvscr (Move to VSCR)
• PowerISA v2.07B, Book I §6.6 — VSCR layout, SAT / NJ semantics.