Sylpheed/tools/ppc-manual/fpu/fctidx.md

fctidx — Floating Convert to Integer Doubleword

Category: Floating-Point · Form: X · Opcode: 0xfc00065c

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
fctid	fctidx	—	Floating Convert to Integer Doubleword
fctid.	fctidx	Rc=1	Floating Convert to Integer Doubleword

Syntax

fctid[Rc] [FD], [FB]

Encoding

fctidx — form X

• Opcode word: 0xfc00065c
• Primary opcode (bits 0–5): 63
• Extended opcode: 814
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

Operands

Field	Role	Description
FB	fctidx: read	Source B floating-point register.
FD	fctidx: write	Destination floating-point register.
CR	fctidx: write (conditional)	Condition-register update. When Rc=1, CR field 0 (or CR6 for vector compares, CR1 for FPU) is updated from the result.
FPSCR	fctidx: write	Floating-Point Status and Control Register.

Register Effects

fctidx

• Reads (always): FB
• Reads (conditional): none
• Writes (always): FD, FPSCR
• Writes (conditional): CR

Status-Register Effects

• fctidx: CR0 ← signed-compare(result, 0) with SO ← XER[SO], when Rc=1.; FPSCR updated per IEEE-754 flags (FX, FEX, FPRF, FR, FI, exceptions).

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

fctidx

• Canary XML: tools/ppc-instructions.xml — search for mnem="fctidx"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_fpu.cc:280
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:70
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:1027

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_fctidx(PPCHIRBuilder& f, const InstrData& i) {
  // frD <- double_to_signed_int64( frB )
  return InstrEmit_fctidxx_(f, i, ROUND_DYNAMIC);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_fpu.cc:261) ──
int InstrEmit_fctidxx_(PPCHIRBuilder& f, const InstrData& i,
                       RoundMode round_mode) {
  auto end = f.NewLabel();
  auto isnan = f.NewLabel();
  Value* v;
  f.BranchTrue(f.IsNan(f.LoadFPR(i.X.RB)), isnan);
  v = f.Convert(f.LoadFPR(i.X.RB), INT64_TYPE, round_mode);
  v = f.Cast(v, FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  f.Branch(end);
  f.MarkLabel(isnan);
  v = f.Cast(f.LoadConstantUint64(0x8000000000000000u), FLOAT64_TYPE);
  f.StoreFPR(i.X.RT, v);
  f.UpdateFPSCR(v, i.X.Rc);
  f.MarkLabel(end);
  return 0;
}

Special Cases & Edge Conditions

• binary64 → 64-bit signed integer, current rounding mode. Result is the integer rounded per FPSCR[RN], packed into the 64-bit FPR as raw bits (the FPR is reinterpreted as an i64 by subsequent stfd/integer code).
• Saturation on out-of-range. PowerPC saturates: large positives → 0x7FFF_FFFF_FFFF_FFFF, large negatives and NaN → 0x8000_0000_0000_0000, setting FPSCR[VXCVI, VX, FX]. Canary's x64 backend reproduces the values — NaN takes an explicit branch to 0x8000…, cvtsd2si yields 0x8000… on overflow, and a fix-up turns that into 0x7FFF… when the input was non-negative — but raises no FPSCR bits (UpdateFPSCR is a stub).
• Rounding follows FPSCR[RN] in Canary. ROUND_DYNAMIC converts with cvtsd2si under the host rounding mode Canary sets from mtfsf/mtfsfi, so default round-to-nearest resolves half-cases to even: 0.5, 1.5, 2.5 → 0, 2, 2, as PowerPC specifies.
• Rounding mode. PPC uses FPSCR[RN] for the rounding direction. Canary honours it: ROUND_DYNAMIC converts with cvtsd2si under the host rounding mode, which Canary loads from FPSCR[RN] whenever the guest writes it through mtfsf/mtfsfi (default round-to-nearest-even).
• Inexact. Sets FPSCR[XX, FX] on any non-integer input on hardware; Canary raises no FPSCR bits (UpdateFPSCR is a stub).
• NaN. Returns sentinel 0x8000_0000_0000_0000 and sets FPSCR[VXCVI]. Canary matches the sentinel through an explicit NaN branch, but does not raise the FPSCR bit.
• Rc=1 (fctid.) copies FPSCR[FX, FEX, VX, OX] into CR1.
• Encoding. X-form, primary 63, XO 814. Reads FRB only.
• Pair with stfd to extract the i64 value to memory or a GPR (Xbox 360 has no direct FPR↔GPR move; round-trip via stack).

Related Instructions

• fctidzx — same conversion but always rounds toward zero (truncation).
• fctiwx, fctiwzx — 32-bit integer variants (saturate to i32 range).
• fcfidx — inverse direction (i64 → binary64).
• mffsx, mtfsfx — control FPSCR[RN].
• stfd, stfiwx — store the integer-bits FPR to memory; stfiwx stores only the low 32 bits (use after fctiwx / fctiwzx).

IBM Reference

• AIX 7.3 — fctid (Floating Convert to Integer Doubleword)
• PowerISA v2.07B, Book I, Chapter 4 — Floating-Point Processor (VXCVI is the invalid-conversion exception bit; saturation sentinel is 0x8000_0000_0000_0000).