Sylpheed/tools/ppc-manual/memory/lmw.md

lmw — Load Multiple Word

Category: Memory · Form: D · Opcode: 0xb8000000

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
lmw	lmw	—	Load Multiple Word

Syntax

(no disassembly template)

Encoding

lmw — form D

• Opcode word: 0xb8000000
• Primary opcode (bits 0–5): 46
• Extended opcode: —
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT	destination GPR (or RS when storing)
11–15	RA	source GPR (0 ⇒ literal 0 for RA0 forms)
16–31	D/SI/UI	16-bit signed or unsigned immediate

Operands

Field	Role	Description

Register Effects

lmw

• Reads (always): none
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

lmw

• Canary XML: tools/ppc-instructions.xml — search for mnem="lmw"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_memory.cc:705
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:132
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:484

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_lmw(PPCHIRBuilder& f, const InstrData& i) {
  Value* b;
  if (i.D.RA == 0) {
    b = f.LoadZeroInt64();
  } else {
    b = f.LoadGPR(i.D.RA);
  }

  for (uint32_t j = 0; j < 32 - i.D.RT; ++j) {
    if (i.D.RT + j == i.D.RA) {
      continue;
    }
    Value* offset = f.LoadConstantInt64(XEEXTS16(i.D.DS) + j * 4);
    Value* rt = f.ZeroExtend(f.ByteSwap(f.LoadOffset(b, offset, INT32_TYPE)),
                             INT64_TYPE);
    f.StoreGPR(i.D.RT + j, rt);
  }
  return 0;
}

Special Cases & Edge Conditions

• Bulk register restore. Loads (32 - RT) consecutive 32-bit words starting at EA into RT, RT+1, …, r31. Used by AIX/PowerPC ABI prologues/epilogues to restore non-volatile GPRs in one instruction. Modern compilers prefer multiple lwz for scheduling; lmw survives in older code and hand-rolled context-switch routines.
• Loop bound from encoding. Canary loops over r(RT)..r31 (j < 32 - RT), matching IBM's "load until r31 inclusive" semantic. With RT = 28, four registers (r28..r31) are loaded. ⚠️ If RA falls in that range (an invalid form), Canary skips the load into RA, so the base register keeps its value.
• Each word is zero-extended. Like lwz, every loaded 32-bit word zero-extends into the destination's 64-bit GPR. The high 32 bits of each r[k] become zero.
• Big-endian read. Word at EA goes to r[RT], word at EA+4 goes to r[RT+1], etc. Each word is itself loaded most-significant-byte-first.
• RA0 semantics. When RA = 0, base is literal zero. Useful for absolute-address restoration.
• Invalid forms. AIX docs declare it invalid for RA to be in the destination range [RT, 31] — a load could overwrite the base register mid-sequence. Canary skips the load into RA in that case, so the base register keeps its value.
• Alignment. PowerISA requires word-aligned EA; an unaligned lmw may raise an alignment exception on real hardware. Canary does not check.
• Performance trap. On modern PowerPC implementations lmw is microcoded — slower than the equivalent sequence of lwz. Compilers avoid it.

Related Instructions

• stmw — symmetric "store multiple words" (the matching epilogue/prologue partner).
• lwz, lwzx — single-word loads; the modern preferred form.
• lswi, lswx — load string (byte-granular bulk transfer).

IBM Reference

• AIX 7.3 — lmw (Load Multiple Word)
• PowerISA v2.07B Book II § "Load and Store Multiple" for invalid-form rules.