Sylpheed/tools/ppc-manual/memory/stvlxl.md

stvlxl — Store Vector Left Indexed LRU

Category: Memory · Form: X · Opcode: 0x7c00070e

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
stvlxl	stvlxl	—	Store Vector Left Indexed LRU
stvlxl128	stvlxl128	—	Store Vector Left Indexed LRU 128

Syntax

stvlxl [VS], [RA0], [RB]
stvlxl128 [VS], [RA0], [RB]

Encoding

stvlxl — form X

• Opcode word: 0x7c00070e
• Primary opcode (bits 0–5): 31
• Extended opcode: 903
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode
6–10	RT/FRT/VRT	destination
11–15	RA/FRA/VRA	source A
16–20	RB/FRB/VRB	source B
21–30	XO	extended opcode (10 bits)
31	Rc	record-form flag

stvlxl128 — form VX128_1

• Opcode word: 0x10000703
• Primary opcode (bits 0–5): 4
• Extended opcode: 1795
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VD128l	destination low 5 bits
11–15	RA	address register
16–20	RB	offset register
21–27	XO	extended opcode
28–29	VD128h	destination high 2 bits
30–31	—	reserved

Operands

Field	Role	Description
VS	stvlxl: read; stvlxl128: read	Source vector register (alias for VD on stores).
RA0	stvlxl: read; stvlxl128: read	Source GPR; when the encoded register number is 0 the operand is the literal 64-bit zero, not r0.
RB	stvlxl: read; stvlxl128: read	Source GPR.

Register Effects

stvlxl

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

stvlxl128

• Reads (always): VS, RA0, RB
• Reads (conditional): none
• Writes (always): none
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

stvlxl

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvlxl"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:271
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:263
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:960

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvlxl(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvlx(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:265) ──
int InstrEmit_stvlx(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvlx_(f, i, i.X.RT, i.X.RA, i.X.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:254) ──
int InstrEmit_stvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) this equals new_value
  //       we could optimize this to prevent the other load/mask, in that case.

  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorLeft(ea, vdr);
  return 0;
}

stvlxl128

• Canary XML: tools/ppc-instructions.xml — search for mnem="stvlxl128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:274
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:264
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:541

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_stvlxl128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvlx128(f, i);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:268) ──
int InstrEmit_stvlx128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_stvlx_(f, i, VX128_1_VD128, i.VX128_1.RA, i.VX128_1.RB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:254) ──
int InstrEmit_stvlx_(PPCHIRBuilder& f, const InstrData& i, uint32_t vd,
                     uint32_t ra, uint32_t rb) {
  // NOTE: if eb == 0 (so 16b aligned) this equals new_value
  //       we could optimize this to prevent the other load/mask, in that case.

  Value* ea = CalculateEA_0(f, ra, rb);

  Value* vdr = f.LoadVR(vd);
  f.StoreVectorLeft(ea, vdr);
  return 0;
}

Special Cases & Edge Conditions

• Same data effect as stvlx, with LRU cache hint. Writes (16 - (EA mod 16)) bytes from the left half of VS starting at EA; right half not stored. The l suffix marks the touched line as least-recently-used.
• Hint ignored under emulation. Canary's stvlxl simply calls its stvlx emitter.
• No alignment masking. The exact EA controls how data is split.
• RA0 semantics. RA = 0 selects literal zero.
• Microsoft Xbox 360 specific. Part of VMX128 / Cell BE.
• Streaming write use case. Pair with stvrxl when the buffer is one-pass output that should not pollute the cache.
• VMX128 sibling (stvlxl128). Identical semantics; alternative operand encoding addressing v0..v127.

Related Instructions

• stvlx, stvlx128 — non-hint variants.
• stvrxl, stvrxl128 — store-right LRU partner.
• stvxl, stvxl128 — aligned LRU vector store.
• lvlxl, lvrxl — symmetric LRU loads.

IBM Reference

• AIX 7.3 — stvlxl (Store Vector Left Indexed Last)
• PowerISA v2.07B Book I "Vector Facility"; Microsoft Xbox 360 XDK for cache-hint behaviour.