Sylpheed/tools/ppc-manual/vmx/vmaxsb.md

vmaxsb — Vector Maximum Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000102

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmaxsb	vmaxsb	—	Vector Maximum Signed Byte

Syntax

vmaxsb [VD], [VA], [VB]

Encoding

vmaxsb — form VX

• Opcode word: 0x10000102
• Primary opcode (bits 0–5): 4
• Extended opcode: 258
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmaxsb: read	Source A vector register.
VB	vmaxsb: read	Source B vector register.
VD	vmaxsb: write	Destination vector register.

Register Effects

vmaxsb

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmaxsb

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmaxsb"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:825
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:352
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:569

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmaxsb(PPCHIRBuilder& f, const InstrData& i) {
  // (VD) <- max((VA), (VB)) (signed int8)
  Value* v = f.VectorMax(f.LoadVR(i.VX.VA), f.LoadVR(i.VX.VB), INT8_TYPE);
  f.StoreVR(i.VX.VD, v);
  return 0;
}

Special Cases & Edge Conditions

• Per-byte signed max. Sixteen byte lanes; VD[i] = max(int8(VA[i]), int8(VB[i])). Lane 0 is the most-significant byte.
• Sign-aware ordering. vmaxsb(0xFF, 0x01) = 0x01 (i.e. max(-1, 1) = 1), versus vmaxub which would return 0xFF. Pick vmaxsb deliberately when both sides are signed.
• No VSCR interaction, no XER, no exceptions. Pure compare-select.
• Common usage. Per-lane clamping with vminsb implements clamp(x, lo, hi) with no branch.
• Aliasing legal. vmaxsb v3, v3, v4 is "raise lower-bound to v4" idiom.
• No VMX128 sibling.

Related Instructions

• vminsb — the matching minimum.
• vmaxub — same width, unsigned max.
• vmaxsh, vmaxsw — signed max at half / word width.
• vcmpgtsb — separate compare-and-mask path.
• vsel — alternative selection style with arbitrary fallbacks.

IBM Reference

• AIX 7.3 — vmaxsb (Vector Maximum Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 6 — Min/Max