Sylpheed/tools/ppc-manual/vmx/vminfp.md

vminfp — Vector Minimum Floating Point

Category: VMX (Altivec) · Form: VX · Opcode: 0x1000044a

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vminfp	vminfp	—	Vector Minimum Floating Point
vminfp128	vminfp128	—	Vector128 Minimum Floating Point

Syntax

vminfp [VD], [VA], [VB]
vminfp128 [VD], [VA], [VB]

Encoding

vminfp — form VX

• Opcode word: 0x1000044a
• Primary opcode (bits 0–5): 4
• Extended opcode: 1098
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

vminfp128 — form VX128

• Opcode word: 0x180002c0
• Primary opcode (bits 0–5): 6
• Extended opcode: 704
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4 or 5)
6–10	VD128l	destination low 5 bits
11–15	VA128l	source A low 5 bits
16–20	VB128l	source B low 5 bits
21	VA128H	source A high bit
22	—	reserved
23–25	VC	optional VC / XO sub-field
26	VA128h	source A middle bit
27	—	reserved
28–29	VD128h	destination high 2 bits
30–31	VB128h	source B high 2 bits

Operands

Field	Role	Description
VA	vminfp: read; vminfp128: read	Source A vector register.
VB	vminfp: read; vminfp128: read	Source B vector register.
VD	vminfp: write; vminfp128: write	Destination vector register.

Register Effects

vminfp

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

vminfp128

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vminfp

• Canary XML: tools/ppc-instructions.xml — search for mnem="vminfp"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:886
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:360
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:642

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vminfp(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vminfp_(f, i.VX.VD, i.VX.VA, i.VX.VB);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:880) ──
int InstrEmit_vminfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- min((VA), (VB))
  Value* v = f.Min(f.LoadVR(va), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

vminfp128

• Canary XML: tools/ppc-instructions.xml — search for mnem="vminfp128"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:889
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:361
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:812

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vminfp128(PPCHIRBuilder& f, const InstrData& i) {
  return InstrEmit_vminfp_(f, VX128_VD128, VX128_VA128, VX128_VB128);
}

// ── delegates to (src/xenia/cpu/ppc/ppc_emit_altivec.cc:880) ──
int InstrEmit_vminfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
  // (VD) <- min((VA), (VB))
  Value* v = f.Min(f.LoadVR(va), f.LoadVR(vb));
  f.StoreVR(vd, v);
  return 0;
}

Special Cases & Edge Conditions

• Per-lane IEEE min. Four word lanes; VD[i] = (VA[i] < VB[i]) ? VA[i] : VB[i].
• NaN propagation. The IBM manual specifies NaN-propagating min — i.e. NaN inputs should yield NaN. Canary's x64 MIN matches: it blends the NaN back in when either lane is NaN (VA's when both are), and takes min(+0, −0) = −0 by OR-ing both operand orders of vminps.
• Sign of zero. Canary's vminfp(+0, -0) returns -0: it ORs both operand orders of vminps. What Xenon returns is unverified.
• VSCR[NJ] denormals. With NJ = 1 (Xenon default), denormal inputs are flushed to ±0 before comparison.
• No VSCR[SAT] change, no XER change, no exceptions.
• Big-endian word lanes. Lane 0 is the most-significant word.
• Aliasing legal. vminfp v3, v3, v4 clamps v3 from above by v4.
• VMX128 sibling (vminfp128). Identical comparator semantics with the extended encoding.

Related Instructions

• vmaxfp — the per-lane maximum.
• vcmpgtfp, vcmpgefp — separate compare-and-mask path.
• vsel — combine masks with arbitrary alternatives.
• vmaddfp — fused multiply-add when the min is part of a polynomial.
• vminsw — integer-word min if the lanes are signed integers.

IBM Reference

• AIX 7.3 — vminfp (Vector Minimum Floating Point)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 5 — Floating-Point Min/Max