Sylpheed/tools/ppc-manual/vmx/vmulosb.md

vmulosb — Vector Multiply Odd Signed Byte

Category: VMX (Altivec) · Form: VX · Opcode: 0x10000108

Assembler Mnemonics

Mnemonic	XML entry	Flags	Description
vmulosb	vmulosb	—	Vector Multiply Odd Signed Byte

Syntax

vmulosb [VD], [VA], [VB]

Encoding

vmulosb — form VX

• Opcode word: 0x10000108
• Primary opcode (bits 0–5): 4
• Extended opcode: 264
• Synchronising: no

Bits	Field	Meaning
0–5	OPCD	primary opcode (4)
6–10	VRT/VD	destination vector register
11–15	VRA/VA	source A vector register
16–20	VRB/VB	source B vector register
21–31	XO	extended opcode (11 bits)

Operands

Field	Role	Description
VA	vmulosb: read	Source A vector register.
VB	vmulosb: read	Source B vector register.
VD	vmulosb: write	Destination vector register.

Register Effects

vmulosb

• Reads (always): VA, VB
• Reads (conditional): none
• Writes (always): VD
• Writes (conditional): none

Status-Register Effects

No condition-register or status-register effects.

Operation (pseudocode)

; No hand-written pseudocode for this instruction yet.
; The authoritative semantics are the Canary emitter snapshot under
; Implementation References; about half of Canary's emitters open
; with the PPC-style definition as a comment (`RD <- (RA) + (RB)`).
; Every side effect is also enumerated in the Register Effects and
; Status-Register Effects tables above.

C Translation Example

/* No hand-written C yet. Translate the Canary emitter snapshot   */
/* under Implementation References; its HIR maps directly:        */
/*   f.LoadGPR(n) / f.StoreGPR(n, v)  -> r[n] / r[n] = v          */
/*   f.LoadFPR / StoreFPR, f.LoadVR / StoreVR -> f[n], v[n]        */
/*   f.Load(ea, T), f.Store(ea, v) -> raw read / write; emitters   */
/*     wrap them in f.ByteSwap for the big-endian guest value      */
/*   f.UpdateCR(n, v)  -> CR field n from v's LOW 32 BITS vs 0     */
/*   f.LoadCA / f.StoreCA -> xer.CA;  f.StoreSAT -> vscr.SAT       */
/*   i.XO.RA, i.D.DS, ... -> the bit-fields listed under Operands  */
/* The Register Effects and Status-Register Effects tables above  */
/* enumerate every side effect a faithful translation must emit.  */

Implementation References

vmulosb

• Canary XML: tools/ppc-instructions.xml — search for mnem="vmulosb"
• Canary emitter: src/xenia/cpu/ppc/ppc_emit_altivec.cc:1091
• Sylpheed opcode: crates/sylpheed-ppc/src/opcode.rs:390
• Sylpheed decoder: crates/sylpheed-ppc/src/decoder.rs:571

Canary emitter (frozen snapshot @ f21ebd49e9)

int InstrEmit_vmulosb(PPCHIRBuilder& f, const InstrData& i) {
  XEINSTRNOTIMPLEMENTED();
  return 1;
}

Special Cases & Edge Conditions

• Odd-lane signed-byte multiply. Only the odd-indexed byte lanes (1, 3, 5, 7, 9, 11, 13, 15 — big-endian numbering) of VA and VB participate. Each pair is treated as signed 8-bit, multiplied, and sign-extended to a signed 16-bit result in the corresponding half-word of VD. Pairing: VD.h[i] = (int8)VA.b[2*i+1] * (int8)VB.b[2*i+1] for i ∈ 0..7.
• Lane-count reduction. 16 byte lanes → 8 half-word lanes.
• No overflow. (-128) * (-128) = 0x4000, (127) * (127) = 0x3F01 — both fit in int16. VSCR[SAT] is not set.
• Pair with vmulesb to get every signed byte × byte product; interleave via vmrghh/vmrglh, or feed into vmsummbm for a multiply-accumulate.
• Signed vs. unsigned distinction. The s in vmulosb makes the product arithmetic: negative operands sign-extend. Compare with vmuloub which zero-extends.
• No Rc, no XER, no VSCR side-effect. No VMX128 sibling.

Related Instructions

• vmulesb — even-lane signed byte multiply.
• vmuloub, vmuleub — unsigned byte twins.
• vmulosh, vmulesh — signed half-word even/odd.
• vmsummbm — fused signed-byte multiply-sum modulo.
• vmrghh, vmrglh — interleave the even/odd half-word results.

IBM Reference

• AIX 7.3 — vmulosb (Vector Multiply Odd Signed Byte)
• IBM AltiVec Technology Programmer's Interface Manual, Chapter 4 — Integer Arithmetic